LPC1767FBD100,551 NXP Semiconductors, LPC1767FBD100,551 Datasheet - Page 86
![IC ARM CORTEX MCU 512K 100-LQFP](/photos/6/65/66516/568-100-lqfp_sot407-1_sml.jpg)
LPC1767FBD100,551
Manufacturer Part Number
LPC1767FBD100,551
Description
IC ARM CORTEX MCU 512K 100-LQFP
Manufacturer
NXP Semiconductors
Series
LPC17xxr
Datasheets
1.LPC1767FBD100551.pdf
(2 pages)
2.LPC1767FBD100551.pdf
(840 pages)
3.LPC1767FBD100551.pdf
(65 pages)
Specifications of LPC1767FBD100,551
Core Processor
ARM® Cortex-M3™
Core Size
32-Bit
Speed
100MHz
Connectivity
Ethernet, I²C, IrDA, Microwire, SPI, SSI, UART/USART
Peripherals
Brown-out Detect/Reset, DMA, I²S, Motor Control PWM, POR, PWM, WDT
Number Of I /o
70
Program Memory Size
512KB (512K x 8)
Program Memory Type
FLASH
Ram Size
64K x 8
Voltage - Supply (vcc/vdd)
2.4 V ~ 3.6 V
Data Converters
A/D 8x12b, D/A 1x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
100-LQFP
Processor Series
LPC17
Core
ARM Cortex M3
3rd Party Development Tools
MDK-ARM, RL-ARM, ULINK2, MCB1760, MCB1760U, MCB1760UME
For Use With
622-1005 - USB IN-CIRCUIT PROG ARM7 LPC2K
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Lead Free Status / Rohs Status
Details
Other names
568-4967
935289808551
935289808551
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
LPC1767FBD100,551
Manufacturer:
NXP Semiconductors
Quantity:
10 000
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NXP Semiconductors
Table 61.
UM10360
User manual
Bit
0
1
2
31:3 -
Name
IAB_PLL1
IAB_USBACT
IAB_CANACT
Interrupt Active Bit Register 1 (IABR1 - 0xE000 E304)
6.5.10 Interrupt Active Bit Register 1 (IABR1 - 0xE000 E304)
Function
PLL1 (USB PLL) Interrupt Active.
Read: 0 indicates that the interrupt is not active, 1 indicates that the interrupt is active.
USB Activity Interrupt Active. See functional description for bit 0.
CAN Activity Interrupt Active. See functional description for bit 0.
Reserved, user software should not write ones to reserved bits. The value read from a reserved bit
is not defined.
The IABR1 register is a read-only register that allows reading the active state of the
second group of peripheral interrupts. This allows determining which peripherals are
asserting an interrupt to the NVIC, and may also be pending if there are enabled.
All information provided in this document is subject to legal disclaimers.
Chapter 6: LPC17xx Nested Vectored Interrupt Controller (NVIC)
Rev. 2 — 19 August 2010
UM10360
© NXP B.V. 2010. All rights reserved.
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