LPC1767FBD100,551 NXP Semiconductors, LPC1767FBD100,551 Datasheet - Page 834

• Manufacturer Part Number: LPC1767FBD100,551
• Description: IC ARM CORTEX MCU 512K 100-LQFP
• Manufacturer: NXP Semiconductors
• Series: LPC17xxr

Specifications of LPC1767FBD100,551

• Core Processor: ARM® Cortex-M3™
• Core Size: 32-Bit
• Speed: 100MHz
• Connectivity: Ethernet, I²C, IrDA, Microwire, SPI, SSI, UART/USART
• Peripherals: Brown-out Detect/Reset, DMA, I²S, Motor Control PWM, POR, PWM, WDT
• Number Of I /o: 70
• Program Memory Size: 512KB (512K x 8)
• Program Memory Type: FLASH
• Ram Size: 64K x 8
• Voltage - Supply (vcc/vdd): 2.4 V ~ 3.6 V
• Data Converters: A/D 8x12b, D/A 1x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 100-LQFP
• Processor Series: LPC17
• Core: ARM Cortex M3
• 3rd Party Development Tools: MDK-ARM, RL-ARM, ULINK2, MCB1760, MCB1760U, MCB1760UME
• For Use With: 622-1005 - USB IN-CIRCUIT PROG ARM7 LPC2K
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Details
• Other names: 568-4967; 935289808551

NXP Semiconductors
30.3
30.4
30.4.1
30.4.2
Chapter 31: LPC17xx General Purpose DMA (GPDMA)
31.1
31.2
31.3
31.4
31.4.1
31.4.1.1
31.4.1.2
31.4.1.3
31.4.1.4
31.4.1.5
31.4.1.6
31.4.1.6.1 Bus and transfer widths . . . . . . . . . . . . . . . . 588
31.4.1.6.2 Endian behavior . . . . . . . . . . . . . . . . . . . . . . 588
31.4.1.6.3 Error conditions . . . . . . . . . . . . . . . . . . . . . . 590
31.4.1.7
31.4.1.8
31.4.1.9
31.4.2
31.4.2.1
31.4.2.2
31.4.2.3
31.5
31.5.1
31.5.2
31.5.3
31.5.4
31.5.5
31.5.6
31.5.7
31.5.8
31.5.9
UM10360
User manual
Pin description . . . . . . . . . . . . . . . . . . . . . . . . 582
Register description . . . . . . . . . . . . . . . . . . . 583
Basic configuration . . . . . . . . . . . . . . . . . . . . 586
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . 586
Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 586
Functional description . . . . . . . . . . . . . . . . . 587
Register description . . . . . . . . . . . . . . . . . . . 593
D/A Converter Register (DACR - 0x4008
C000) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 583
D/A Converter Control register (DACCTRL -
0x4008 C004) . . . . . . . . . . . . . . . . . . . . . . . . 583
DMA controller functional description . . . . . . 587
AHB slave interface . . . . . . . . . . . . . . . . . . . 587
Control logic and register bank . . . . . . . . . . . 588
DMA request and response interface . . . . . . 588
Channel logic and channel register bank . . . 588
Interrupt request . . . . . . . . . . . . . . . . . . . . . . 588
AHB master interface . . . . . . . . . . . . . . . . . . 588
Channel hardware . . . . . . . . . . . . . . . . . . . . 591
DMA request priority . . . . . . . . . . . . . . . . . . . 591
Interrupt generation . . . . . . . . . . . . . . . . . . . 591
DMA system connections . . . . . . . . . . . . . . . 591
DMA request signals . . . . . . . . . . . . . . . . . . 591
DMA response signals . . . . . . . . . . . . . . . . . 591
DMA request connections . . . . . . . . . . . . . . 592
DMA Interrupt Status register (DMACIntStat -
0x5000 4000) . . . . . . . . . . . . . . . . . . . . . . . . 595
DMA Interrupt Terminal Count Request Status
register (DMACIntTCStat - 0x5000 4004). . . 595
DMA Interrupt Terminal Count Request Clear
register (DMACIntTCClear - 0x5000 4008) . 595
DMA Interrupt Error Status register
(DMACIntErrStat - 0x5000 400C) . . . . . . . . . 595
DMA Interrupt Error Clear register
(DMACIntErrClr - 0x5000 4010) . . . . . . . . . . 596
DMA Raw Interrupt Terminal Count Status register
(DMACRawIntTCStat - 0x5000 4014). . . . . . 596
DMA Raw Error Interrupt Status register
(DMACRawIntErrStat - 0x5000 4018). . . . . . 596
DMA Enabled Channel register
(DMACEnbldChns - 0x5000 401C). . . . . . . . 597
DMA Software Burst Request register
(DMACSoftBReq - 0x5000 4020) . . . . . . . . . 597
All information provided in this document is subject to legal disclaimers.
Rev. 2 — 19 August 2010
30.4.3
30.5
30.5.1
30.5.2
31.5.10
31.5.11
31.5.12
31.5.13
31.5.14
31.5.15
31.5.16
31.5.17
31.5.18
31.5.19
31.5.20
31.5.20.1 Protection and access information. . . . . . . . 602
31.5.21
31.5.21.1 Lock control . . . . . . . . . . . . . . . . . . . . . . . . . 606
31.5.21.2 Transfer type . . . . . . . . . . . . . . . . . . . . . . . . 606
31.6
31.6.1
31.6.1.1
31.6.1.2
31.6.1.3
31.6.1.4
31.6.1.5
31.6.1.6
31.6.1.7
31.6.2
Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . 584
Using the DMA controller . . . . . . . . . . . . . . . 607
D/A Converter Counter Value register
(DACCNTVAL - 0x4008 C008). . . . . . . . . . . 584
DMA counter . . . . . . . . . . . . . . . . . . . . . . . . 584
Double buffering. . . . . . . . . . . . . . . . . . . . . . 584
DMA Software Single Request register
(DMACSoftSReq - 0x5000 4024). . . . . . . . . 598
DMA Software Last Burst Request register
(DMACSoftLBReq - 0x5000 4028). . . . . . . . 598
DMA Software Last Single Request register
(DMACSoftLSReq - 0x5000 402C) . . . . . . . 598
DMA Configuration register (DMACConfig -
0x5000 4030) . . . . . . . . . . . . . . . . . . . . . . . . 599
DMA Synchronization register (DMACSync -
0x5000 4034) . . . . . . . . . . . . . . . . . . . . . . . . 599
DMA Request Select register (DMAReqSel -
0x400F C1C4) . . . . . . . . . . . . . . . . . . . . . . . 600
DMA Channel registers . . . . . . . . . . . . . . . . 600
DMA Channel Source Address registers
(DMACCxSrcAddr - 0x5000 41x0). . . . . . . . 601
DMA Channel Destination Address registers
(DMACCxDestAddr - 0x5000 41x4). . . . . . . 601
DMA Channel Linked List Item registers
(DMACCxLLI - 0x5000 41x8). . . . . . . . . . . . 601
DMA channel control registers (DMACCxControl -
0x5000 41xC). . . . . . . . . . . . . . . . . . . . . . . . 602
DMA Channel Configuration registers
(DMACCxConfig - 0x5000 41x0) . . . . . . . . . 604
Programming the DMA controller. . . . . . . . . 607
Enabling the DMA controller . . . . . . . . . . . . 607
Disabling the DMA controller . . . . . . . . . . . . 607
Enabling a DMA channel . . . . . . . . . . . . . . . 607
Disabling a DMA channel. . . . . . . . . . . . . . . 607
Disabling a DMA channel and losing data in the
FIFO. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 607
Disabling the DMA channel without losing data in
the FIFO. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 607
Setting up a new DMA transfer . . . . . . . . . . 607
Halting a DMA channel . . . . . . . . . . . . . . . . 608
Programming a DMA channel . . . . . . . . . . . 608
Flow control . . . . . . . . . . . . . . . . . . . . . . . . . 608
Chapter 35: Supplementary information
UM10360
© NXP B.V. 2010. All rights reserved.
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