LPC1767FBD100,551 NXP Semiconductors, LPC1767FBD100,551 Datasheet - Page 69
![IC ARM CORTEX MCU 512K 100-LQFP](/photos/6/65/66516/568-100-lqfp_sot407-1_sml.jpg)
LPC1767FBD100,551
Manufacturer Part Number
LPC1767FBD100,551
Description
IC ARM CORTEX MCU 512K 100-LQFP
Manufacturer
NXP Semiconductors
Series
LPC17xxr
Datasheets
1.LPC1767FBD100551.pdf
(2 pages)
2.LPC1767FBD100551.pdf
(840 pages)
3.LPC1767FBD100551.pdf
(65 pages)
Specifications of LPC1767FBD100,551
Core Processor
ARM® Cortex-M3™
Core Size
32-Bit
Speed
100MHz
Connectivity
Ethernet, I²C, IrDA, Microwire, SPI, SSI, UART/USART
Peripherals
Brown-out Detect/Reset, DMA, I²S, Motor Control PWM, POR, PWM, WDT
Number Of I /o
70
Program Memory Size
512KB (512K x 8)
Program Memory Type
FLASH
Ram Size
64K x 8
Voltage - Supply (vcc/vdd)
2.4 V ~ 3.6 V
Data Converters
A/D 8x12b, D/A 1x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
100-LQFP
Processor Series
LPC17
Core
ARM Cortex M3
3rd Party Development Tools
MDK-ARM, RL-ARM, ULINK2, MCB1760, MCB1760U, MCB1760UME
For Use With
622-1005 - USB IN-CIRCUIT PROG ARM7 LPC2K
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Lead Free Status / Rohs Status
Details
Other names
568-4967
935289808551
935289808551
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
LPC1767FBD100,551
Manufacturer:
NXP Semiconductors
Quantity:
10 000
- Current page: 69 of 840
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NXP Semiconductors
5.3 Register description
UM10360
User manual
5.2.2 Flash programming Issues
Since the flash memory does not allow accesses during programming and erase
operations, it is necessary for the flash accelerator to force the CPU to wait if a memory
access to a flash address is requested while the flash memory is busy with a
programming operation. Under some conditions, this delay could result in a Watchdog
time-out. The user will need to be aware of this possibility and take steps to insure that an
unwanted Watchdog reset does not cause a system failure while programming or erasing
the flash memory.
In order to preclude the possibility of stale data being read from the flash memory, the
LPC17xx flash accelerator buffers are automatically invalidated at the beginning of any
flash programming or erase operation. Any subsequent read from a flash address will
cause a new fetch to be initiated after the flash operation has completed.
The flash accelerator is controlled by the register shown in
descriptions follow.
Table 48.
[1]
Name
FLASHCFG
Reset Value reflects the data stored in defined bits only. It does not include reserved bits content.
Summary of flash accelerator registers
Description
Flash Accelerator Configuration Register.
Controls flash access timing. See
All information provided in this document is subject to legal disclaimers.
Rev. 2 — 19 August 2010
Table
Chapter 5: LPC17xx Flash accelerator
49.
Access Reset
R/W
Table
48. More detailed
value
0x303A 0x400F C000
UM10360
© NXP B.V. 2010. All rights reserved.
[1]
Address
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