LPC1767FBD100,551 NXP Semiconductors, LPC1767FBD100,551 Datasheet - Page 622

• Manufacturer Part Number: LPC1767FBD100,551
• Description: IC ARM CORTEX MCU 512K 100-LQFP
• Manufacturer: NXP Semiconductors
• Series: LPC17xxr

Specifications of LPC1767FBD100,551

• Core Processor: ARM® Cortex-M3™
• Core Size: 32-Bit
• Speed: 100MHz
• Connectivity: Ethernet, I²C, IrDA, Microwire, SPI, SSI, UART/USART
• Peripherals: Brown-out Detect/Reset, DMA, I²S, Motor Control PWM, POR, PWM, WDT
• Number Of I /o: 70
• Program Memory Size: 512KB (512K x 8)
• Program Memory Type: FLASH
• Ram Size: 64K x 8
• Voltage - Supply (vcc/vdd): 2.4 V ~ 3.6 V
• Data Converters: A/D 8x12b, D/A 1x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 100-LQFP
• Processor Series: LPC17
• Core: ARM Cortex M3
• 3rd Party Development Tools: MDK-ARM, RL-ARM, ULINK2, MCB1760, MCB1760U, MCB1760UME
• For Use With: 622-1005 - USB IN-CIRCUIT PROG ARM7 LPC2K
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Details
• Other names: 568-4967; 935289808551

NXP Semiconductors
UM10360
User manual
Table 569. Code Read Protection hardware/software interaction
If any CRP mode is enabled and access to the chip is allowed via the ISP, an unsupported
or restricted ISP command will be terminated with return code
CODE_READ_PROTECTION_ENABLED.
CRP option
None
CRP1
CRP2
CRP3
User Code
Valid
No
Yes
Yes
No
Yes
Yes
No
Yes
Yes
No
Yes
All information provided in this document is subject to legal disclaimers.
Chapter 32: LPC17xx Flash memory interface and programming
Rev. 2 — 19 August 2010
P2.10 pin at
reset
X
High
Low
x
High
Low
x
High
x
Low
x
JTAG enabled LPC17xx
Yes
Yes
Yes
No
No
No
No
No
No
No
No
enters ISP
mode
Yes
No
Yes
Yes
No
Yes
Yes
No
Yes
Yes
No
UM10360
© NXP B.V. 2010. All rights reserved.
partial flash
update in ISP
mode
Yes
NA
Yes
Yes
NA
Yes
No
NA
No
No
NA
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