LPC1767FBD100,551 NXP Semiconductors, LPC1767FBD100,551 Datasheet - Page 486

• Manufacturer Part Number: LPC1767FBD100,551
• Description: IC ARM CORTEX MCU 512K 100-LQFP
• Manufacturer: NXP Semiconductors
• Series: LPC17xxr

Specifications of LPC1767FBD100,551

• Core Processor: ARM® Cortex-M3™
• Core Size: 32-Bit
• Speed: 100MHz
• Connectivity: Ethernet, I²C, IrDA, Microwire, SPI, SSI, UART/USART
• Peripherals: Brown-out Detect/Reset, DMA, I²S, Motor Control PWM, POR, PWM, WDT
• Number Of I /o: 70
• Program Memory Size: 512KB (512K x 8)
• Program Memory Type: FLASH
• Ram Size: 64K x 8
• Voltage - Supply (vcc/vdd): 2.4 V ~ 3.6 V
• Data Converters: A/D 8x12b, D/A 1x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 100-LQFP
• Processor Series: LPC17
• Core: ARM Cortex M3
• 3rd Party Development Tools: MDK-ARM, RL-ARM, ULINK2, MCB1760, MCB1760U, MCB1760UME
• For Use With: 622-1005 - USB IN-CIRCUIT PROG ARM7 LPC2K
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Details
• Other names: 568-4967; 935289808551

NXP Semiconductors
Table 420: I
UM10360
User manual
I2SDAI
Fig 106. 4-wire transmitter slave mode sharing the receiver bit clock and WS
[5]
0
0
0
0
1
1
1
I2SRXMODE
2
S receive modes
0 0 0 0
0 0 1 0
0 1 0 0
1 0 0 0
0 0 0 0
0 0 1 0
0 1 0 0
[3:0]
Description
Typical receiver master mode. See
The
The receive clock source is the fractional rate divider.
The WS used is the internally generated RX_WS.
The RX_MCLK pin is not enabled for output.
Receiver master mode sharing the transmitter reference clock. See
The
The receive clock source is TX_REF.
The WS used is the internally generated RX_WS.
The RX_MCLK pin is not enabled for output.
4-wire receiver master mode sharing the transmitter bit clock and WS. See
The
The receive clock source is the TX bit clock.
The WS used is the internally generated TX_WS.
The RX_MCLK pin is not enabled for output.
Receiver master mode with RX_MCLK output. See
The
The receive clock source is the fractional rate divider.
The WS used is the internally generated RX_WS.
The RX_MCLK pin is enabled for output.
Typical receiver slave mode. See
The
The receive clock source is the RX_CLK pin.
The WS used is the RX_WS pin.
Receiver slave mode sharing the transmitter reference clock. See
The
The receive clock source is TX_REF.
The WS used is the RX_WS pin.
This is a 4-wire receiver slave mode sharing the transmitter bit clock and WS. See
The
The receive clock source is the TX bit clock.
The WS used is TX_WS ref.
I
I
I
I
I
I
I
2
2
2
2
2
2
2
S
S
S
S
S
S
S
receive function operates as a master.
receive function operates as a master.
receive function operates as a master.
receive function operates as a master.
receive function operates as a slave.
receive function operates as a slave.
receive function operates as a slave.
RX bit clock
All information provided in this document is subject to legal disclaimers.
Rev. 2 — 19 August 2010
peripheral
(transmit)
block
I
2
S
Figure
Figure
RX_WS ref
110.
107.
Figure
I2STX_SDA
I2STX_WS
107.
Figure
Figure
Chapter 20: LPC17xx I2S
111.
108.
Figure
UM10360
© NXP B.V. 2010. All rights reserved.
109.
Figure
486 of 840
112.