LPC1767FBD100,551 NXP Semiconductors, LPC1767FBD100,551 Datasheet - Page 658

• Manufacturer Part Number: LPC1767FBD100,551
• Description: IC ARM CORTEX MCU 512K 100-LQFP
• Manufacturer: NXP Semiconductors
• Series: LPC17xxr

Specifications of LPC1767FBD100,551

• Core Processor: ARM® Cortex-M3™
• Core Size: 32-Bit
• Speed: 100MHz
• Connectivity: Ethernet, I²C, IrDA, Microwire, SPI, SSI, UART/USART
• Peripherals: Brown-out Detect/Reset, DMA, I²S, Motor Control PWM, POR, PWM, WDT
• Number Of I /o: 70
• Program Memory Size: 512KB (512K x 8)
• Program Memory Type: FLASH
• Ram Size: 64K x 8
• Voltage - Supply (vcc/vdd): 2.4 V ~ 3.6 V
• Data Converters: A/D 8x12b, D/A 1x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 100-LQFP
• Processor Series: LPC17
• Core: ARM Cortex M3
• 3rd Party Development Tools: MDK-ARM, RL-ARM, ULINK2, MCB1760, MCB1760U, MCB1760UME
• For Use With: 622-1005 - USB IN-CIRCUIT PROG ARM7 LPC2K
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Details
• Other names: 568-4967; 935289808551

NXP Semiconductors
UM10360
User manual
34.2.3.8 Instruction width selection
Table 615. Condition code suffixes
Section
R0 = ABS(R1).
Section
values R0 is greater than R1 and R2 is greater than R3.
Example: Absolute value:
Example: Compare and update value:
There are many instructions that can generate either a 16-bit encoding or a 32-bit
encoding depending on the operands and destination register specified. For some of
these instructions, you can force a specific instruction size by using an instruction width
suffix. The .W suffix forces a 32-bit instruction encoding. The .N suffix forces a 16-bit
instruction encoding.
If you specify an instruction width suffix and the assembler cannot generate an instruction
encoding of the requested width, it generates an error.
Remark: In some cases it might be necessary to specify the .W suffix, for example if the
operand is the label of an instruction or literal data, as in the case of branch instructions.
This is because the assembler might not automatically generate the right size encoding.
To use an instruction width suffix, place it immediately after the instruction mnemonic and
condition code, if any.
suffix.
Suffix
PL
VS
VC
HI
LS
GE
LT
GT
LE
AL
setting flags
shows the use of a conditional instruction to find the absolute value of a number.
shows the use of conditional instructions to update the value of R4 if the signed
IT
RSBMI
ITT
CMPGT
MOVGT
All information provided in this document is subject to legal disclaimers.
MI
R0, R1, #0
GT
R2, R3
R4, R5
Flags
N = 0
V = 1
V = 0
C = 1 and Z = 0
C = 0 or Z = 1
N = V
N ! = V
Z = 0 and N = V
Z = 1 and N ! = V
Can have any
value
Section 34.2.3.8.1
Rev. 2 — 19 August 2010
; IT instruction for the two GT conditions
; If 'greater than', compare R2 and R3, setting flags
; If still 'greater than', do R4 = R5
MOVS
; IT instruction for the negative condition
; If negative, R0 = -R1
Meaning
Positive or zero
Overflow
No overflow
Higher, unsigned >
Lower or same, unsigned ≤
Greater than or equal, signed ≥
Less than, signed <
Greater than, signed >
Less than or equal, signed ≤
Always. This is the default when no suffix is specified.
R0, R1
shows instructions with the instruction width
Chapter 34: Appendix: Cortex-M3 user guide
CMP
R0, R1
; R0 = R1, setting flags
; Compare R0 and R1,
UM10360
© NXP B.V. 2010. All rights reserved.
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