LPC1767FBD100,551 NXP Semiconductors, LPC1767FBD100,551 Datasheet - Page 511

• Manufacturer Part Number: LPC1767FBD100,551
• Description: IC ARM CORTEX MCU 512K 100-LQFP
• Manufacturer: NXP Semiconductors
• Series: LPC17xxr

Specifications of LPC1767FBD100,551

• Core Processor: ARM® Cortex-M3™
• Core Size: 32-Bit
• Speed: 100MHz
• Connectivity: Ethernet, I²C, IrDA, Microwire, SPI, SSI, UART/USART
• Peripherals: Brown-out Detect/Reset, DMA, I²S, Motor Control PWM, POR, PWM, WDT
• Number Of I /o: 70
• Program Memory Size: 512KB (512K x 8)
• Program Memory Type: FLASH
• Ram Size: 64K x 8
• Voltage - Supply (vcc/vdd): 2.4 V ~ 3.6 V
• Data Converters: A/D 8x12b, D/A 1x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 100-LQFP
• Processor Series: LPC17
• Core: ARM Cortex M3
• 3rd Party Development Tools: MDK-ARM, RL-ARM, ULINK2, MCB1760, MCB1760U, MCB1760UME
• For Use With: 622-1005 - USB IN-CIRCUIT PROG ARM7 LPC2K
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Details
• Other names: 568-4967; 935289808551

NXP Semiconductors
UM10360
User manual
Fig 119. PWM block diagram
REGISTER 0
REGISTER 1
REGISTER 2
REGISTER 3
REGISTER 4
REGISTER 5
REGISTER 6
MATCH
MATCH
MATCH
MATCH
MATCH
MATCH
MATCH
LOAD ENABLE REGISTER
TIMER CONTROL REGISTER
CAPTURE CONTROL REGISTER
CONTROL
M[6:0]
INTERRUPT
CAPTURE[1:0]
STOP ON MATCH
RESET ON MATCH
LOAD[1:0]
MATCH CONTROL REGISTER
disable
master
INTERRUPT REGISTER
CAPTURE REGISTER 0
CAPTURE REGISTER 1
RESERVED
RESERVED
reset
SHADOW REGISTER 0
LOAD ENABLE
SHADOW REGISTER 1
LOAD ENABLE
SHADOW REGISTER 2
LOAD ENABLE
SHADOW REGISTER 3
LOAD ENABLE
SHADOW REGISTER 4
LOAD ENABLE
SHADOW REGISTER 5
LOAD ENABLE
SHADOW REGISTER 6
LOAD ENABLE
enable
CLEAR
Match 0
All information provided in this document is subject to legal disclaimers.
Rev. 2 — 19 August 2010
=
CSN
=
=
PRESCALE REGISTER
PRESCALE COUNTER
Chapter 24: LPC17xx Pulse Width Modulator (PWM)
MAXVAL
TIMER COUNTER
=
=
CE
=
TCI
=
Match 2
Match 3
Match 0
Match 1
Match 4
PWM CONTROL REGISTER
Match 5
Match 6
PWMENA1..6
MUX
MUX
MUX
MUX
MUX
PWMSEL2
PWMSEL3
PWMSEL4
PWMSEL5
PWMSEL6
UM10360
© NXP B.V. 2010. All rights reserved.
R
R
R
R
R
R
S
S
S
S
S
S
EN
EN
EN
EN
EN
EN
Q
Q
Q
Q
Q
Q
PWMSEL2..6
PWM1
PWMENA1
PWM2
PWMENA2
PWM3
PWMENA3
PWM4
PWMENA4
PWM5
PWMENA5
PWM6
PWMENA6
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