LPC1767FBD100,551 NXP Semiconductors, LPC1767FBD100,551 Datasheet - Page 691
LPC1767FBD100,551
Manufacturer Part Number
LPC1767FBD100,551
Description
IC ARM CORTEX MCU 512K 100-LQFP
Manufacturer
NXP Semiconductors
Series
LPC17xxr
Datasheets
1.LPC1767FBD100551.pdf
(2 pages)
2.LPC1767FBD100551.pdf
(840 pages)
3.LPC1767FBD100551.pdf
(65 pages)
Specifications of LPC1767FBD100,551
Core Processor
ARM® Cortex-M3™
Core Size
32-Bit
Speed
100MHz
Connectivity
Ethernet, I²C, IrDA, Microwire, SPI, SSI, UART/USART
Peripherals
Brown-out Detect/Reset, DMA, I²S, Motor Control PWM, POR, PWM, WDT
Number Of I /o
70
Program Memory Size
512KB (512K x 8)
Program Memory Type
FLASH
Ram Size
64K x 8
Voltage - Supply (vcc/vdd)
2.4 V ~ 3.6 V
Data Converters
A/D 8x12b, D/A 1x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
100-LQFP
Processor Series
LPC17
Core
ARM Cortex M3
3rd Party Development Tools
MDK-ARM, RL-ARM, ULINK2, MCB1760, MCB1760U, MCB1760UME
For Use With
622-1005 - USB IN-CIRCUIT PROG ARM7 LPC2K
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Lead Free Status / Rohs Status
Details
Other names
568-4967
935289808551
935289808551
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
LPC1767FBD100,551
Manufacturer:
NXP Semiconductors
Quantity:
10 000
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NXP Semiconductors
UM10360
User manual
34.2.5.9.1 Syntax
34.2.5.9.2 Operation
34.2.5.9.3 Restrictions
34.2.5.9.4 Condition flags
34.2.5.9.5 Examples
34.2.5.9 TST and TEQ
Test bits and Test Equivalence.
TST{cond} Rn, Operand2
TEQ{cond} Rn, Operand2
where:
cond is an optional condition code, see
Rn is the register holding the first operand.
Operand2 is a flexible second operand. See
These instructions test the value in a register against Operand2. They update the
condition flags based on the result, but do not write the result to a register.
The TST instruction performs a bitwise AND operation on the value in Rn and the value of
Operand2. This is the same as the ANDS instruction, except that it discards the result.
To test whether a bit of Rn is 0 or 1, use the TST instruction with an Operand2 constant that
has that bit set to 1 and all other bits cleared to 0.
The TEQ instruction performs a bitwise Exclusive OR operation on the value in Rn and the
value of Operand2. This is the same as the EORS instruction, except that it discards the
result.
Use the TEQ instruction to test if two values are equal without affecting the V or C flags.
TEQ is also useful for testing the sign of a value. After the comparison, the N flag is the
logical Exclusive OR of the sign bits of the two operands.
Do not use SP and do not use PC.
These instructions:
•
•
•
update the N and Z flags according to the result
can update the C flag during the calculation of Operand2, see
do not affect the V flag.
TST
TEQEQ
All information provided in this document is subject to legal disclaimers.
R0, #0x3F8 ; Perform bitwise AND of R0 value to 0x3F8,
R10, R9
Rev. 2 — 19 August 2010
; APSR is updated but result is discarded
; Conditionally test if value in R10 is equal to
; value in R9, APSR is updated but result is discarded
Section 34.2.3.7 “Conditional
Chapter 34: Appendix: Cortex-M3 user guide
Section 34.2.3.3
for details of the options.
Section 34.2.3.3
execution”.
UM10360
© NXP B.V. 2010. All rights reserved.
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