LPC1767FBD100,551 NXP Semiconductors, LPC1767FBD100,551 Datasheet - Page 509

• Manufacturer Part Number: LPC1767FBD100,551
• Description: IC ARM CORTEX MCU 512K 100-LQFP
• Manufacturer: NXP Semiconductors
• Series: LPC17xxr

Specifications of LPC1767FBD100,551

• Core Processor: ARM® Cortex-M3™
• Core Size: 32-Bit
• Speed: 100MHz
• Connectivity: Ethernet, I²C, IrDA, Microwire, SPI, SSI, UART/USART
• Peripherals: Brown-out Detect/Reset, DMA, I²S, Motor Control PWM, POR, PWM, WDT
• Number Of I /o: 70
• Program Memory Size: 512KB (512K x 8)
• Program Memory Type: FLASH
• Ram Size: 64K x 8
• Voltage - Supply (vcc/vdd): 2.4 V ~ 3.6 V
• Data Converters: A/D 8x12b, D/A 1x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 100-LQFP
• Processor Series: LPC17
• Core: ARM Cortex M3
• 3rd Party Development Tools: MDK-ARM, RL-ARM, ULINK2, MCB1760, MCB1760U, MCB1760UME
• For Use With: 622-1005 - USB IN-CIRCUIT PROG ARM7 LPC2K
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Details
• Other names: 568-4967; 935289808551

24.1 Basic configuration
24.2 Features
UM10360
User manual
The PWM is configured using the following registers:
1. Power: In the PCONP register
2. Peripheral clock: In the PCLKSEL0 register
3. Pins: Select PWM pins through the PINSEL registers. Select pin modes for port pins
4. Interrupts: See registers PWM1MCR
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UM10360
Chapter 24: LPC17xx Pulse Width Modulator (PWM)
Rev. 2 — 19 August 2010
Remark: On reset, the PWM is enabled (PCPWM1 = 1).
with PWM1 functions through the PINMODE registers
match and capture events. Interrupts are enabled in the NVIC using the appropriate
Interrupt Set Enable register.
Counter or Timer operation (may use the peripheral clock or one of the capture inputs
as the clock source).
Seven match registers allow up to 6 single edge controlled or 3 double edge
controlled PWM outputs, or a mix of both types. The match registers also allow:
– Continuous operation with optional interrupt generation on match.
– Stop timer on match with optional interrupt generation.
– Reset timer on match with optional interrupt generation.
Supports single edge controlled and/or double edge controlled PWM outputs. Single
edge controlled PWM outputs all go high at the beginning of each cycle unless the
output is a constant low. Double edge controlled PWM outputs can have either edge
occur at any position within a cycle. This allows for both positive going and negative
going pulses.
Pulse period and width can be any number of timer counts. This allows complete
flexibility in the trade-off between resolution and repetition rate. All PWM outputs will
occur at the same repetition rate.
Double edge controlled PWM outputs can be programmed to be either positive going
or negative going pulses.
Match register updates are synchronized with pulse outputs to prevent generation of
erroneous pulses. Software must "release" new match values before they can
become effective.
May be used as a standard timer if the PWM mode is not enabled.
A 32-bit Timer/Counter with a programmable 32-bit prescaler.
Two 32-bit capture channels take a snapshot of the timer value when an input signal
transitions. A capture event may also optionally generate an interrupt.
All information provided in this document is subject to legal disclaimers.
Rev. 2 — 19 August 2010
(Table
(Table
46), set bit PCPWM1.
(Table
449) and PWM1CCR
40), select PCLK_PWM1.
(Section
8.5).
(Table
© NXP B.V. 2010. All rights reserved.
User manual
450) for
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