LPC1767FBD100,551 NXP Semiconductors, LPC1767FBD100,551 Datasheet - Page 650

• Manufacturer Part Number: LPC1767FBD100,551
• Description: IC ARM CORTEX MCU 512K 100-LQFP
• Manufacturer: NXP Semiconductors
• Series: LPC17xxr

Specifications of LPC1767FBD100,551

• Core Processor: ARM® Cortex-M3™
• Core Size: 32-Bit
• Speed: 100MHz
• Connectivity: Ethernet, I²C, IrDA, Microwire, SPI, SSI, UART/USART
• Peripherals: Brown-out Detect/Reset, DMA, I²S, Motor Control PWM, POR, PWM, WDT
• Number Of I /o: 70
• Program Memory Size: 512KB (512K x 8)
• Program Memory Type: FLASH
• Ram Size: 64K x 8
• Voltage - Supply (vcc/vdd): 2.4 V ~ 3.6 V
• Data Converters: A/D 8x12b, D/A 1x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 100-LQFP
• Processor Series: LPC17
• Core: ARM Cortex M3
• 3rd Party Development Tools: MDK-ARM, RL-ARM, ULINK2, MCB1760, MCB1760U, MCB1760UME
• For Use With: 622-1005 - USB IN-CIRCUIT PROG ARM7 LPC2K
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Details
• Other names: 568-4967; 935289808551

NXP Semiconductors
UM10360
User manual
34.2.2 Intrinsic functions
34.2.3 About the instruction descriptions
ANSI cannot directly access some Cortex-M3 instructions. This section describes intrinsic
functions that can generate these instructions, provided by the CMIS and that might be
provided by a C compiler. If a C compiler does not support an appropriate intrinsic
function, you might have to use inline assembler to access some instructions.
The CMSIS provides the following intrinsic functions to generate instructions that ANSI
cannot directly access:
Table 613. CMSIS intrinsic functions to generate some Cortex-M3 instructions
The CMSIS also provides a number of functions for accessing the special registers using
MRS and MSR instructions:
Table 614. CMSIS intrinsic functions to access the special registers
The following sections give more information about using the instructions:
Instruction
CPSIE I
CPSID I
CPSIE F
CPSID F
ISB
DSB
DMB
REV
REV16
REVSH
RBIT
SEV
WFE
WFI
Special register
PRIMASK
FAULTMASK
BASEPRI
CONTROL
MSP
PSP
All information provided in this document is subject to legal disclaimers.
CMSIS intrinsic function
void __enable_irq(void)
void __disable_irq(void)
void __enable_fault_irq(void)
void __disable_fault_irq(void)
void __ISB(void)
void __DSB(void)
void __DMB(void)
uint32_t __REV(uint32_t int value)
uint32_t __REV16(uint32_t int value)
uint32_t __REVSH(uint32_t int value)
uint32_t __RBIT(uint32_t int value)
void __SEV(void)
void __WFE(void)
void __WFI(void)
Access
Read
Write
Read
Write
Read
Write
Read
Write
Read
Write
Read
Write
Rev. 2 — 19 August 2010
CMSIS function
uint32_t __get_PRIMASK (void)
void __set_PRIMASK (uint32_t value)
uint32_t __get_FAULTMASK (void)
void __set_FAULTMASK (uint32_t value)
uint32_t __get_BASEPRI (void)
void __set_BASEPRI (uint32_t value)
uint32_t __get_CONTROL (void)
void __set_CONTROL (uint32_t value)
uint32_t __get_MSP (void)
void __set_MSP (uint32_t TopOfMainStack)
uint32_t __get_PSP (void)
void __set_PSP (uint32_t TopOfProcStack)
Chapter 34: Appendix: Cortex-M3 user guide
UM10360
© NXP B.V. 2010. All rights reserved.
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