LPC1767FBD100,551 NXP Semiconductors, LPC1767FBD100,551 Datasheet - Page 289
LPC1767FBD100,551
Manufacturer Part Number
LPC1767FBD100,551
Description
IC ARM CORTEX MCU 512K 100-LQFP
Manufacturer
NXP Semiconductors
Series
LPC17xxr
Datasheets
1.LPC1767FBD100551.pdf
(2 pages)
2.LPC1767FBD100551.pdf
(840 pages)
3.LPC1767FBD100551.pdf
(65 pages)
Specifications of LPC1767FBD100,551
Core Processor
ARM® Cortex-M3™
Core Size
32-Bit
Speed
100MHz
Connectivity
Ethernet, I²C, IrDA, Microwire, SPI, SSI, UART/USART
Peripherals
Brown-out Detect/Reset, DMA, I²S, Motor Control PWM, POR, PWM, WDT
Number Of I /o
70
Program Memory Size
512KB (512K x 8)
Program Memory Type
FLASH
Ram Size
64K x 8
Voltage - Supply (vcc/vdd)
2.4 V ~ 3.6 V
Data Converters
A/D 8x12b, D/A 1x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
100-LQFP
Processor Series
LPC17
Core
ARM Cortex M3
3rd Party Development Tools
MDK-ARM, RL-ARM, ULINK2, MCB1760, MCB1760U, MCB1760UME
For Use With
622-1005 - USB IN-CIRCUIT PROG ARM7 LPC2K
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Lead Free Status / Rohs Status
Details
Other names
568-4967
935289808551
935289808551
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
LPC1767FBD100,551
Manufacturer:
NXP Semiconductors
Quantity:
10 000
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NXP Semiconductors
UM10360
User manual
Fig 41. State transitions implemented in software during B-device switching from peripheral to host
Note that only the subset of B-device HNP states and state transitions supported by
hardware are shown. Software is responsible for implementing all of the HNP states.
Figure 41
polled, but this is not necessary if the corresponding interrupt is enabled.
Following are code examples that show how the actions in
The examples assume that ISP1302 is being used as the external OTG transceiver.
Remove D+ pull-up
/* Remove D+ pull-up through ISP1302 */
OTG_I2C_TX = 0x15A; // Send ISP1302 address, R/W=0
OTG_I2C_TX = 0x007; // Send OTG Control (Clear) register address
OTG_I2C_TX = 0x201; // Clear DP_PULLUP bit, send STOP condition
no
no
when host sends SET_FEATURE
may appear to imply that the interrupt bits such as REMOVE_PU should be
HNP_SUCCESS set?
with b_hnp_enable,
HNP_FAILURE set?
set B_HNP_TRACK
REMOVE_PU set?
set PU_REMOVED
remove D+ pull-up,
All information provided in this document is subject to legal disclaimers.
b_peripheral
b_wait_acon
b_host
go to
go to
yes
yes
no
Rev. 2 — 19 August 2010
yes
add D+ pull-up
b_peripheral
go to
Chapter 13: LPC17xx USB OTG
Figure 41
are accomplished.
UM10360
© NXP B.V. 2010. All rights reserved.
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