LPC1767FBD100,551 NXP Semiconductors, LPC1767FBD100,551 Datasheet - Page 772

• Manufacturer Part Number: LPC1767FBD100,551
• Description: IC ARM CORTEX MCU 512K 100-LQFP
• Manufacturer: NXP Semiconductors
• Series: LPC17xxr

Specifications of LPC1767FBD100,551

• Core Processor: ARM® Cortex-M3™
• Core Size: 32-Bit
• Speed: 100MHz
• Connectivity: Ethernet, I²C, IrDA, Microwire, SPI, SSI, UART/USART
• Peripherals: Brown-out Detect/Reset, DMA, I²S, Motor Control PWM, POR, PWM, WDT
• Number Of I /o: 70
• Program Memory Size: 512KB (512K x 8)
• Program Memory Type: FLASH
• Ram Size: 64K x 8
• Voltage - Supply (vcc/vdd): 2.4 V ~ 3.6 V
• Data Converters: A/D 8x12b, D/A 1x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 100-LQFP
• Processor Series: LPC17
• Core: ARM Cortex M3
• 3rd Party Development Tools: MDK-ARM, RL-ARM, ULINK2, MCB1760, MCB1760U, MCB1760UME
• For Use With: 622-1005 - USB IN-CIRCUIT PROG ARM7 LPC2K
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Details
• Other names: 568-4967; 935289808551

NXP Semiconductors
Table 660. Priority grouping
[1]
UM10360
User manual
PRIGROUP
b010
b011
b100
b101
b110
b111
PRI_ n [7:0] field showing the binary point. x denotes a group priority field bit, and y denotes a subpriority field bit. Bits [2:0] are not used
in LPC17xx devices.
34.4.3.6.1 Binary point
34.4.3.7 System Control Register
Interrupt priority level value, PRI_N[7:0]
Binary point
bxxxxx.000
bxxxx.y000
bxxx.yy000
bxx.yyy000
bx.yyyy000
b.yyyyy000
Table 659. AIRCR bit assignments
The PRIGROUP field indicates the position of the binary point that splits the PRI_n fields
in the Interrupt Priority Registers into separate group priority and subpriority fields.
Table 660
Remark: Determining preemption of an exception uses only the group priority field, see
Section 34.3.3.6 “Interrupt priority
The SCR controls features of entry to and exit from low power state. See the register
summary in
Bits
[2]
[1]
[0]
[1]
Name
SYSRESETREQ
VECTCLRACTIVE WO
VECTRESET
shows how the PRIGROUP value controls this split.
Table 654
Group priority
bits
[7:3]
[7:4]
[7:5]
[7:6]
[7]
None
All information provided in this document is subject to legal disclaimers.
Rev. 2 — 19 August 2010
for its attributes. The bit assignments are shown in
Type
WO
WO
Subpriority bits
none
[4:3]
[5:3]
[6:3]
[7:3]
[3]
grouping”.
Function
System reset request:
0 = no system reset request
1 = asserts a signal to the outer system that requests a
reset.
This is intended to force a large system reset of all major
components except for debug. Note: support for
SYSRESETREQ is not included in LPC17xx devices.
This bit reads as 0.
Reserved for Debug use. This bit reads as 0. When writing
to the register you must write 0 to this bit, otherwise
behavior is Unpredictable.
Reserved for Debug use. This bit reads as 0. When writing
to the register you must write 0 to this bit, otherwise
behavior is Unpredictable.
Chapter 34: Appendix: Cortex-M3 user guide
Number of
Group priorities
32
16
8
4
2
1
Subpriorities
1
2
4
8
16
32
UM10360
© NXP B.V. 2010. All rights reserved.
Table
661.
772 of 840