LPC1767FBD100,551 NXP Semiconductors, LPC1767FBD100,551 Datasheet - Page 272

• Manufacturer Part Number: LPC1767FBD100,551
• Description: IC ARM CORTEX MCU 512K 100-LQFP
• Manufacturer: NXP Semiconductors
• Series: LPC17xxr

Specifications of LPC1767FBD100,551

• Core Processor: ARM® Cortex-M3™
• Core Size: 32-Bit
• Speed: 100MHz
• Connectivity: Ethernet, I²C, IrDA, Microwire, SPI, SSI, UART/USART
• Peripherals: Brown-out Detect/Reset, DMA, I²S, Motor Control PWM, POR, PWM, WDT
• Number Of I /o: 70
• Program Memory Size: 512KB (512K x 8)
• Program Memory Type: FLASH
• Ram Size: 64K x 8
• Voltage - Supply (vcc/vdd): 2.4 V ~ 3.6 V
• Data Converters: A/D 8x12b, D/A 1x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 100-LQFP
• Processor Series: LPC17
• Core: ARM Cortex M3
• 3rd Party Development Tools: MDK-ARM, RL-ARM, ULINK2, MCB1760, MCB1760U, MCB1760UME
• For Use With: 622-1005 - USB IN-CIRCUIT PROG ARM7 LPC2K
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Details
• Other names: 568-4967; 935289808551

NXP Semiconductors
Table 254. USB Host register address definitions
[1]
UM10360
User manual
Name
HcControlHeadED
HcControlCurrentED
HcBulkHeadED
HcBulkCurrentED
HcDoneHead
HcFmInterval
HcFmRemaining
HcFmNumber
HcPeriodicStart
HcLSThreshold
HcRhDescriptorA
HcRhDescriptorB
HcRhStatus
HcRhPortStatus[1]
HcRhPortStatus[2]
Module_ID/Ver_Rev_ID
The R/W column in
a) Registers marked ‘R’ for access will return their current value when read.
b) Registers marked ‘R/W’ allow both read and write.
12.4.2.2 USB Host Register Definitions
Table 254
Refer to the OHCI specification document on the Compaq website for register definitions.
Address
0x5000 C020
0x5000 C024
0x5000 C028
0x5000 C02C
0x5000 C030
0x5000 C034
0x5000 C038
0x5000 C03C
0x5000 C040
0x5000 C044
0x5000 C048
0x5000 C04C
0x5000 C050
0x5000 C054
0x5000 C0FC
0x5000 C058
lists the accessibility of the register:
All information provided in this document is subject to legal disclaimers.
R/W
R/W
R/W
R/W
R/W
R
R/W
R
R
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R
[1]
Rev. 2 — 19 August 2010
Function
Contains the physical address of the first endpoint
descriptor of the control list.
Contains the physical address of the current endpoint
descriptor of the control list
Contains the physical address of the first endpoint
descriptor of the bulk list.
Contains the physical address of the current endpoint
descriptor of the bulk list.
Contains the physical address of the last transfer
descriptor added to the ‘Done’ queue.
Defines the bit time interval in a frame and the full speed
maximum packet size which would not cause an
overrun.
A 14-bit counter showing the bit time remaining in the
current frame.
Contains a 16-bit counter and provides the timing
reference among events happening in the HC and the
HCD.
Contains a programmable 14-bit value which determines
the earliest time HC should start processing a periodic
list.
Contains 11-bit value which is used by the HC to
determine whether to commit to transfer a maximum of
8-byte LS packet before EOF.
First of the two registers which describes the
characteristics of the root hub.
Second of the two registers which describes the
characteristics of the Root Hub.
This register is divided into two parts. The lower D-word
represents the hub status field and the upper word
represents the hub status change field.
Controls and reports the port events on a per-port basis. 0x0
Controls and reports the port events on a per port basis. 0x0
IP number, where yy (0x00) is unique version number
and zz (0x00) is a unique revision number.
…continued
Chapter 12: LPC17xx USB Host controller
UM10360
© NXP B.V. 2010. All rights reserved.
Reset value
0x0
0x0
0x0
0x0
0x0
0x2EDF
0x0
0x0
0x0
0x628h
0xFF000902
0x60000h
0x0
0x3505yyzz
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