LPC1767FBD100,551 NXP Semiconductors, LPC1767FBD100,551 Datasheet - Page 209
LPC1767FBD100,551
Manufacturer Part Number
LPC1767FBD100,551
Description
IC ARM CORTEX MCU 512K 100-LQFP
Manufacturer
NXP Semiconductors
Series
LPC17xxr
Datasheets
1.LPC1767FBD100551.pdf
(2 pages)
2.LPC1767FBD100551.pdf
(840 pages)
3.LPC1767FBD100551.pdf
(65 pages)
Specifications of LPC1767FBD100,551
Core Processor
ARM® Cortex-M3™
Core Size
32-Bit
Speed
100MHz
Connectivity
Ethernet, I²C, IrDA, Microwire, SPI, SSI, UART/USART
Peripherals
Brown-out Detect/Reset, DMA, I²S, Motor Control PWM, POR, PWM, WDT
Number Of I /o
70
Program Memory Size
512KB (512K x 8)
Program Memory Type
FLASH
Ram Size
64K x 8
Voltage - Supply (vcc/vdd)
2.4 V ~ 3.6 V
Data Converters
A/D 8x12b, D/A 1x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
100-LQFP
Processor Series
LPC17
Core
ARM Cortex M3
3rd Party Development Tools
MDK-ARM, RL-ARM, ULINK2, MCB1760, MCB1760U, MCB1760UME
For Use With
622-1005 - USB IN-CIRCUIT PROG ARM7 LPC2K
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Lead Free Status / Rohs Status
Details
Other names
568-4967
935289808551
935289808551
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
LPC1767FBD100,551
Manufacturer:
NXP Semiconductors
Quantity:
10 000
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NXP Semiconductors
UM10360
User manual
10.18.2 Types of CPU access
10.18.3 Overall bandwidth
This gives a total rate of 30.5 Mbps for the traffic generated by the Ethernet DMA function.
This gives a total rate of 36 Mbps for the traffic generated by the Ethernet DMA function.
Overall traffic on the AHB is the sum of DMA access rates and CPU access rates, which
comes to approximately 66.5 MB/s.
The peak bandwidth requirement can be somewhat higher due to the use of small
memory buffers, in order to hold often used addresses (e.g. the station address) for
example. Driver software can determine how to build frames in an efficient manner that
does not overutilize the AHB.
The bandwidth available on the AHB bus depends on the system clock frequency. As an
example, assume that the system clock is set at 60 MHz. All or nearly all of bus accesses
related to the Ethernet will be word transfers. The raw AHB bandwidth can be
approximated as 4 bytes per two system clocks, which equals 2 times the system clock
rate. With a 60 MHz system clock, the bandwidth is 120 MB/s, giving about 55% utilization
•
•
•
•
•
Rx status write:
– Receive status occupies 2 words (8 bytes) of memory and is written once for each
– Two word write happens once every 64 bytes (16 words) of received data.
– This gives 1/8 of the data rate, which = 1.5625 Mbps.
Tx data read:
– Data transmitted in an Ethernet frame, the size is variable.
– Basic Ethernet rate = 12.5 Mbps.
Rx data write:
– Data to be received in an Ethernet frame, the size is variable.
– Basic Ethernet rate = 12.5 Mbps.
Accesses that mirror each of the DMA access types:
– All or part of status values must be read, and all or part of descriptors need to be
– This gives roughly the same or slightly lower rate as the combined DMA functions,
Access to registers in the Ethernet block:
– The CPU must read the RxProduceIndex, TxConsumeIndex, and IntStatus
– 7 word read/writes once every 64 bytes (16 words) of transmitted and received
– This gives 7/16 of the data rate, which = 5.4688 Mbps.
use of a descriptor.
written after each use, transmitted data must be stored in the memory by the CPU,
and eventually received data must be retrieved from the memory by the CPU.
which = 30.5 Mbps.
registers, and both read and write the RxConsumeIndex and TxProduceIndex
registers.
data.
All information provided in this document is subject to legal disclaimers.
Rev. 2 — 19 August 2010
Chapter 10: LPC17xx Ethernet
UM10360
© NXP B.V. 2010. All rights reserved.
209 of 840
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