LPC1767FBD100,551 NXP Semiconductors, LPC1767FBD100,551 Datasheet - Page 557
LPC1767FBD100,551
Manufacturer Part Number
LPC1767FBD100,551
Description
IC ARM CORTEX MCU 512K 100-LQFP
Manufacturer
NXP Semiconductors
Series
LPC17xxr
Datasheets
1.LPC1767FBD100551.pdf
(2 pages)
2.LPC1767FBD100551.pdf
(840 pages)
3.LPC1767FBD100551.pdf
(65 pages)
Specifications of LPC1767FBD100,551
Core Processor
ARM® Cortex-M3™
Core Size
32-Bit
Speed
100MHz
Connectivity
Ethernet, I²C, IrDA, Microwire, SPI, SSI, UART/USART
Peripherals
Brown-out Detect/Reset, DMA, I²S, Motor Control PWM, POR, PWM, WDT
Number Of I /o
70
Program Memory Size
512KB (512K x 8)
Program Memory Type
FLASH
Ram Size
64K x 8
Voltage - Supply (vcc/vdd)
2.4 V ~ 3.6 V
Data Converters
A/D 8x12b, D/A 1x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
100-LQFP
Processor Series
LPC17
Core
ARM Cortex M3
3rd Party Development Tools
MDK-ARM, RL-ARM, ULINK2, MCB1760, MCB1760U, MCB1760UME
For Use With
622-1005 - USB IN-CIRCUIT PROG ARM7 LPC2K
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Lead Free Status / Rohs Status
Details
Other names
568-4967
935289808551
935289808551
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
LPC1767FBD100,551
Manufacturer:
NXP Semiconductors
Quantity:
10 000
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NXP Semiconductors
Table 505: QEI Interrupt Enable Clear register (QEIIEC - address 0x400B CFD8) bit description
UM10360
User manual
Bit
0
1
2
3
4
5
6
7
8
9
10
11
12
31:13
Symbol
INX_EN
TIM_EN
VELC_EN
DIR_EN
ERR_EN
ENCLK_EN
POS0_Int
POS1_Int
POS2_Int
REV_Int
POS0REV_Int Combined position 0 and revolution count interrupt. Set when both the POS0_Int bit is set
POS1REV_Int Combined position 1 and revolution count interrupt. Set when both the POS1_Int bit is set
POS2REV_Int Combined position 2 and revolution count interrupt. Set when both the POS2_Int bit is set
-
26.6.4.6 QEI Interrupt Enable Clear register (QEIIEC - 0x400B CFD8)
Writing a 1 to a bit in this register clears the corresponding bit in the QEI Interrupt Enable
register (QEIIE).
Description
Indicates that an index pulse was detected.
Indicates that a velocity timer overflow occurred
Indicates that captured velocity is less than compare velocity.
Indicates that a change of direction was detected.
Indicates that an encoder phase error was detected.
Indicates that and encoder clock pulse was detected.
Indicates that the position 0 compare value is equal to the current position.
Indicates that the position 1compare value is equal to the current position.
Indicates that the position 2 compare value is equal to the current position.
Indicates that the index compare value is equal to the current index count.
and the REV_Int is set.
and the REV_Int is set.
and the REV_Int is set.
reserved
All information provided in this document is subject to legal disclaimers.
Rev. 2 — 19 August 2010
Chapter 26: LPC17xx Quadrature Encoder Interface (QEI)
UM10360
© NXP B.V. 2010. All rights reserved.
557 of 840
Reset
value
0
0
0
0
0
0
0
0
0
0
0
0
0
0
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