LPC1767FBD100,551 NXP Semiconductors, LPC1767FBD100,551 Datasheet - Page 738

• Manufacturer Part Number: LPC1767FBD100,551
• Description: IC ARM CORTEX MCU 512K 100-LQFP
• Manufacturer: NXP Semiconductors
• Series: LPC17xxr

Specifications of LPC1767FBD100,551

• Core Processor: ARM® Cortex-M3™
• Core Size: 32-Bit
• Speed: 100MHz
• Connectivity: Ethernet, I²C, IrDA, Microwire, SPI, SSI, UART/USART
• Peripherals: Brown-out Detect/Reset, DMA, I²S, Motor Control PWM, POR, PWM, WDT
• Number Of I /o: 70
• Program Memory Size: 512KB (512K x 8)
• Program Memory Type: FLASH
• Ram Size: 64K x 8
• Voltage - Supply (vcc/vdd): 2.4 V ~ 3.6 V
• Data Converters: A/D 8x12b, D/A 1x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 100-LQFP
• Processor Series: LPC17
• Core: ARM Cortex M3
• 3rd Party Development Tools: MDK-ARM, RL-ARM, ULINK2, MCB1760, MCB1760U, MCB1760UME
• For Use With: 622-1005 - USB IN-CIRCUIT PROG ARM7 LPC2K
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Details
• Other names: 568-4967; 935289808551

NXP Semiconductors
UM10360
User manual
34.3.2.2 Memory system ordering of memory accesses
The different ordering requirements for Device and Strongly-ordered memory mean that
the memory system can buffer a write to Device memory, but must not buffer a write to
Strongly-ordered memory.
The additional memory attributes include.
For most memory accesses caused by explicit memory access instructions, the memory
system does not guarantee that the order in which the accesses complete matches the
program order of the instructions, providing this does not affect the behavior of the
instruction sequence. Normally, if correct program execution depends on two memory
accesses completing in program order, software must insert a memory barrier instruction
between the memory access instructions, see
However, the memory system does guarantee some ordering of accesses to Device and
Strongly-ordered memory. For two memory access instructions A1 and A2, if A1 occurs
before A2 in program order, the ordering of the memory accesses caused by two
instructions is:
Where:
•
•
•
•
•
‘—’ means that the memory system does not guarantee the ordering of the accesses.
Normal: The processor can re-order transactions for efficiency, or perform speculative
reads.
Device: The processor preserves transaction order relative to other transactions to
Device or Strongly-ordered memory.
Strongly-ordered: The processor preserves transaction order relative to all other
transactions.
Shareable
For a shareable memory region, the memory system provides data synchronization
between bus masters in a system with multiple bus masters, for example, a processor
with a DMA controller.
Strongly-ordered memory is always shareable.
If multiple bus masters can access a non-shareable memory region, software must
ensure data coherency between the bus masters.
Execute Never (XN)
Means the processor prevents instruction accesses. Any attempt to fetch an
instruction from an XN region causes a memory management fault exception.
Device access, non-shareable
A1
Device access, shareable
All information provided in this document is subject to legal disclaimers.
Strongly-ordered access
Rev. 2 — 19 August 2010
Normal access
A2
Normal
access
Chapter 34: Appendix: Cortex-M3 user guide
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34.3.2.4.
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UM10360
© NXP B.V. 2010. All rights reserved.
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