LPC1767FBD100,551 NXP Semiconductors, LPC1767FBD100,551 Datasheet - Page 579
LPC1767FBD100,551
Manufacturer Part Number
LPC1767FBD100,551
Description
IC ARM CORTEX MCU 512K 100-LQFP
Manufacturer
NXP Semiconductors
Series
LPC17xxr
Datasheets
1.LPC1767FBD100551.pdf
(2 pages)
2.LPC1767FBD100551.pdf
(840 pages)
3.LPC1767FBD100551.pdf
(65 pages)
Specifications of LPC1767FBD100,551
Core Processor
ARM® Cortex-M3™
Core Size
32-Bit
Speed
100MHz
Connectivity
Ethernet, I²C, IrDA, Microwire, SPI, SSI, UART/USART
Peripherals
Brown-out Detect/Reset, DMA, I²S, Motor Control PWM, POR, PWM, WDT
Number Of I /o
70
Program Memory Size
512KB (512K x 8)
Program Memory Type
FLASH
Ram Size
64K x 8
Voltage - Supply (vcc/vdd)
2.4 V ~ 3.6 V
Data Converters
A/D 8x12b, D/A 1x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
100-LQFP
Processor Series
LPC17
Core
ARM Cortex M3
3rd Party Development Tools
MDK-ARM, RL-ARM, ULINK2, MCB1760, MCB1760U, MCB1760UME
For Use With
622-1005 - USB IN-CIRCUIT PROG ARM7 LPC2K
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Lead Free Status / Rohs Status
Details
Other names
568-4967
935289808551
935289808551
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
LPC1767FBD100,551
Manufacturer:
NXP Semiconductors
Quantity:
10 000
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NXP Semiconductors
Table 533: A/D Status register (AD0INTEN - address 0x4003 400C) bit description
Table 534: A/D Data Registers (AD0DR0 to AD0DR7 - 0x4003 4010 to 0x4003 402C) bit description
UM10360
User manual
Bit
3
4
5
6
7
8
31:17 -
Bit
3:0
15:4
29:16
30
31
Symbol
ADINTEN3
ADINTEN4
ADINTEN5
ADINTEN6
ADINTEN7
ADGINTEN
Symbol
-
RESULT
-
OVERRUN This bit is 1 in burst mode if the results of one or more conversions was (were) lost and
DONE
29.5.4 A/D Data Registers (AD0DR0 to AD0DR7 - 0x4003 4010 to
Description
Reserved, user software should not write ones to reserved bits. The value read from a
reserved bit is not defined.
When DONE is 1, this field contains a binary fraction representing the voltage on the AD0[n]
pin, as it falls within the range of V
the input pin was less than, equal to, or close to that on V
voltage on the input was close to, equal to, or greater than that on V
Reserved, user software should not write ones to reserved bits. The value read from a
reserved bit is not defined.
overwritten before the conversion that produced the result in the RESULT bits.This bit is
cleared by reading this register.
This bit is set to 1 when an A/D conversion completes. It is cleared when this register is read. NA
Value
0
1
0
1
0
1
0
1
0
1
1
0x4003 402C)
The A/D Data Registers hold the result of the last conversion for each A/D channel, when
an A/D conversion is complete. They also include the flags that indicate when a
conversion has been completed and when a conversion overrun has occurred.
Results of ADC conversion can be read in one of two ways. One is to use the A/D Global
Data Register to read all data from the ADC. Another is to use the A/D Channel Data
Registers. It is important to use one method consistently because the DONE and
OVERRUN flags can otherwise get out of synch between the AD0GDR and the A/D
Channel Data Registers, potentially causing erroneous interrupts or DMA activity.
0
Description
Completion of a conversion on ADC channel 3 will not generate an interrupt.
Completion of a conversion on ADC channel 3 will generate an interrupt.
Completion of a conversion on ADC channel 4 will not generate an interrupt.
Completion of a conversion on ADC channel 4 will generate an interrupt.
Completion of a conversion on ADC channel 5 will not generate an interrupt.
Completion of a conversion on ADC channel 5 will generate an interrupt.
Completion of a conversion on ADC channel 6 will not generate an interrupt.
Completion of a conversion on ADC channel 6 will generate an interrupt.
Completion of a conversion on ADC channel 7 will not generate an interrupt.
Completion of a conversion on ADC channel 7 will generate an interrupt.
Only the individual ADC channels enabled by ADINTEN7:0 will generate
interrupts.
Only the global DONE flag in ADDR is enabled to generate an interrupt.
Reserved, user software should not write ones to reserved bits. The value
read from a reserved bit is not defined.
All information provided in this document is subject to legal disclaimers.
Rev. 2 — 19 August 2010
REFP
Chapter 29: LPC17xx Analog-to-Digital Converter (ADC)
to V
REFN
. Zero in the field indicates that the voltage on
REFN
, while 0xFFF indicates that the
REFP
.
UM10360
© NXP B.V. 2010. All rights reserved.
Reset
value
0
0
0
0
0
1
NA
579 of 840
Reset
value
NA
NA
NA
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