LPC1767FBD100,551 NXP Semiconductors, LPC1767FBD100,551 Datasheet - Page 712
![IC ARM CORTEX MCU 512K 100-LQFP](/photos/6/65/66516/568-100-lqfp_sot407-1_sml.jpg)
LPC1767FBD100,551
Manufacturer Part Number
LPC1767FBD100,551
Description
IC ARM CORTEX MCU 512K 100-LQFP
Manufacturer
NXP Semiconductors
Series
LPC17xxr
Datasheets
1.LPC1767FBD100551.pdf
(2 pages)
2.LPC1767FBD100551.pdf
(840 pages)
3.LPC1767FBD100551.pdf
(65 pages)
Specifications of LPC1767FBD100,551
Core Processor
ARM® Cortex-M3™
Core Size
32-Bit
Speed
100MHz
Connectivity
Ethernet, I²C, IrDA, Microwire, SPI, SSI, UART/USART
Peripherals
Brown-out Detect/Reset, DMA, I²S, Motor Control PWM, POR, PWM, WDT
Number Of I /o
70
Program Memory Size
512KB (512K x 8)
Program Memory Type
FLASH
Ram Size
64K x 8
Voltage - Supply (vcc/vdd)
2.4 V ~ 3.6 V
Data Converters
A/D 8x12b, D/A 1x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
100-LQFP
Processor Series
LPC17
Core
ARM Cortex M3
3rd Party Development Tools
MDK-ARM, RL-ARM, ULINK2, MCB1760, MCB1760U, MCB1760UME
For Use With
622-1005 - USB IN-CIRCUIT PROG ARM7 LPC2K
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Lead Free Status / Rohs Status
Details
Other names
568-4967
935289808551
935289808551
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
LPC1767FBD100,551
Manufacturer:
NXP Semiconductors
Quantity:
10 000
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NXP Semiconductors
UM10360
User manual
34.2.9.4.1 Syntax
34.2.9.4.2 Operation
34.2.9.4.3 Restrictions
34.2.9.4.4 Condition flags
34.2.9.4.5 Examples
34.2.9.4 TBB and TBH
Table Branch Byte and Table Branch Halfword.
TBB [Rn, Rm]
TBH [Rn, Rm, LSL #1]
where:
Rn is the register containing the address of the table of branch lengths.
If Rn is PC, then the address of the table is the address of the byte immediately following
the TBB or TBH instruction.
Rm is the index register. This contains an index into the table. For halfword tables, LSL #1
doubles the value in Rm to form the right offset into the table.
These instructions cause a PC-relative forward branch using a table of single byte offsets
for TBB, or halfword offsets for TBH. Rn provides a pointer to the table, and Rm supplies an
index into the table. For TBB the branch offset is twice the unsigned value of the byte
returned from the table. and for TBH the branch offset is twice the unsigned value of the
halfword returned from the table. The branch occurs to the address at that offset from the
address of the byte immediately after the TBB or TBH instruction.
The restrictions are:
These instructions do not change the flags.
•
•
•
Rn must not be SP
Rm must not be SP and must not be PC
when any of these instructions is used inside an IT block, it must be the last
instruction of the IT block.
Case1
; an instruction sequence follows
Case2
; an instruction sequence follows
Case3
; an instruction sequence follows
BranchTable_Byte
ADR.W R0, BranchTable_Byte
TBB
DCB
DCB
DCB
All information provided in this document is subject to legal disclaimers.
[R0, R1]
0
((Case2-Case1)/2) ; Case2 offset calculation
((Case3-Case1)/2) ; Case3 offset calculation
Rev. 2 — 19 August 2010
; R1 is the index, R0 is the base address of the
; branch table
; Case1 offset calculation
Chapter 34: Appendix: Cortex-M3 user guide
UM10360
© NXP B.V. 2010. All rights reserved.
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