LPC1767FBD100,551 NXP Semiconductors, LPC1767FBD100,551 Datasheet - Page 767

• Manufacturer Part Number: LPC1767FBD100,551
• Description: IC ARM CORTEX MCU 512K 100-LQFP
• Manufacturer: NXP Semiconductors
• Series: LPC17xxr

Specifications of LPC1767FBD100,551

• Core Processor: ARM® Cortex-M3™
• Core Size: 32-Bit
• Speed: 100MHz
• Connectivity: Ethernet, I²C, IrDA, Microwire, SPI, SSI, UART/USART
• Peripherals: Brown-out Detect/Reset, DMA, I²S, Motor Control PWM, POR, PWM, WDT
• Number Of I /o: 70
• Program Memory Size: 512KB (512K x 8)
• Program Memory Type: FLASH
• Ram Size: 64K x 8
• Voltage - Supply (vcc/vdd): 2.4 V ~ 3.6 V
• Data Converters: A/D 8x12b, D/A 1x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 100-LQFP
• Processor Series: LPC17
• Core: ARM Cortex M3
• 3rd Party Development Tools: MDK-ARM, RL-ARM, ULINK2, MCB1760, MCB1760U, MCB1760UME
• For Use With: 622-1005 - USB IN-CIRCUIT PROG ARM7 LPC2K
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Details
• Other names: 568-4967; 935289808551

NXP Semiconductors
Table 654. Summary of the system control block registers
[1]
[2]
UM10360
User manual
Address
0xE000E008
0xE000ED00
0xE000ED04
0xE000ED08
0xE000ED0C
0xE000ED10
0xE000ED14
0xE000ED18
0xE000ED1C
0xE000ED20
0xE000ED24
0xE000ED28
0xE000ED28
0xE000ED29
0xE000ED2A
0xE000ED2C
0xE000ED34
0xE000ED38
See the register description for more information.
A subregister of the CFSR.
34.4.3.1 The CMSIS mapping of the Cortex-M3 SCB registers
34.4.3.2 Auxiliary Control Register
34.4.3 System control block
Name
ACTLR
CPUID
ICSR
VTOR
AIRCR
SCR
CCR
SHPR1
SHPR2
SHPR3
SHCRS
CFSR
MMSR
BFSR
UFSR
HFSR
MMFAR
BFAR
The System control block (SCB) provides system implementation information, and
system control. This includes configuration, control, and reporting of the system
exceptions. The system control block registers are:
To improve software efficiency, the CMSIS simplifies the SCB register presentation. In the
CMSIS, the byte array SHP[0] to SHP[12] corresponds to the registers SHPR1-SHPR3.
The ACTLR provides disable bits for the following processor functions:
See the register summary in
shown in
•
•
•
[2]
[2]
[2]
IT folding
write buffer use for accesses to the default memory map
interruption of multi-cycle instructions.
Table
Type
RW
RO
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
655.
All information provided in this document is subject to legal disclaimers.
[1]
[1]
Rev. 2 — 19 August 2010
Table 654
Required
privilege
Privileged
Privileged
Privileged
Privileged
Privileged
Privileged
Privileged
Privileged
Privileged
Privileged
Privileged
Privileged
Privileged
Privileged
Privileged
Privileged
Privileged
Privileged
for the ACTLR attributes. The bit assignments are
Chapter 34: Appendix: Cortex-M3 user guide
Reset
value
0x00000000
0x412FC230
0x00000000
0x00000000
0xFA050000
0x00000000
0x00000200
0x00000000
0x00000000
0x00000000
0x00000000
0x00000000
0x00
0x00
0x0000
0x00000000
Undefined
Undefined
UM10360
© NXP B.V. 2010. All rights reserved.
Description
Table 655
Table 656
Table 657
Table 658
Table 659
Table 661
Table 662
Table 664
Table 665
Table 666
Table 667
Section 34.4.3.11
Table 668
Table 669
Table 670
Table 671
Table 672
Table 673
767 of 840