LPC1767FBD100,551 NXP Semiconductors, LPC1767FBD100,551 Datasheet - Page 321

• Manufacturer Part Number: LPC1767FBD100,551
• Description: IC ARM CORTEX MCU 512K 100-LQFP
• Manufacturer: NXP Semiconductors
• Series: LPC17xxr

Specifications of LPC1767FBD100,551

• Core Processor: ARM® Cortex-M3™
• Core Size: 32-Bit
• Speed: 100MHz
• Connectivity: Ethernet, I²C, IrDA, Microwire, SPI, SSI, UART/USART
• Peripherals: Brown-out Detect/Reset, DMA, I²S, Motor Control PWM, POR, PWM, WDT
• Number Of I /o: 70
• Program Memory Size: 512KB (512K x 8)
• Program Memory Type: FLASH
• Ram Size: 64K x 8
• Voltage - Supply (vcc/vdd): 2.4 V ~ 3.6 V
• Data Converters: A/D 8x12b, D/A 1x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 100-LQFP
• Processor Series: LPC17
• Core: ARM Cortex M3
• 3rd Party Development Tools: MDK-ARM, RL-ARM, ULINK2, MCB1760, MCB1760U, MCB1760UME
• For Use With: 622-1005 - USB IN-CIRCUIT PROG ARM7 LPC2K
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Details
• Other names: 568-4967; 935289808551

NXP Semiconductors
Table 290: UART1 Receiver Buffer Register (U1RBR - address 0x4001 0000 when DLAB = 0) bit description
Table 291: UART1 Transmitter Holding Register (U1THR - address 0x4001 0000 when DLAB = 0) bit description
UM10360
User manual
Bit
7:0
31:8
Bit
7:0
31:8
Symbol Description
RBR
-
Symbol Description
THR
-
15.4.1 UART1 Receiver Buffer Register (U1RBR - 0x4001 0000, when
15.4.2 UART1 Transmitter Holding Register (U1THR - 0x4001 0000 when
15.4.3 UART1 Divisor Latch LSB and MSB Registers (U1DLL - 0x4001 0000
The UART1 Receiver Buffer Register contains the oldest received byte in the UART1 RX
FIFO.
Reserved, the value read from a reserved bit is not defined.
Writing to the UART1 Transmit Holding Register causes the data to be stored in the UART1
transmit FIFO. The byte will be sent when it reaches the bottom of the FIFO and the
transmitter is available.
Reserved, user software should not write ones to reserved bits.
DLAB = 0)
The U1RBR is the top byte of the UART1 RX FIFO. The top byte of the RX FIFO contains
the oldest character received and can be read via the bus interface. The LSB (bit 0)
represents the “oldest” received data bit. If the character received is less than 8 bits, the
unused MSBs are padded with zeroes.
The Divisor Latch Access Bit (DLAB) in U1LCR must be zero in order to access the
U1RBR. The U1RBR is always read-only.
Since PE, FE and BI bits correspond to the byte sitting on the top of the RBR FIFO (i.e.
the one that will be read in the next read from the RBR), the right approach for fetching the
valid pair of received byte and its status bits is first to read the content of the U1LSR
register, and then to read a byte from the U1RBR.
DLAB = 0)
The write-only U1THR is the top byte of the UART1 TX FIFO. The top byte is the newest
character in the TX FIFO and can be written via the bus interface. The LSB represents the
first bit to transmit.
The Divisor Latch Access Bit (DLAB) in U1LCR must be zero in order to access the
U1THR. The U1THR is write-only.
and U1DLM - 0x4001 0004, when DLAB = 1)
The UART1 Divisor Latch is part of the UART1 Baud Rate Generator and holds the value
used, along with the Fractional Divider, to divide the APB clock (PCLK) in order to produce
the baud rate clock, which must be 16x the desired baud rate. The U1DLL and U1DLM
registers together form a 16-bit divisor where U1DLL contains the lower 8 bits of the
divisor and U1DLM contains the higher 8 bits of the divisor. A 0x0000 value is treated like
a 0x0001 value as division by zero is not allowed.The Divisor Latch Access Bit (DLAB) in
U1LCR must be one in order to access the UART1 Divisor Latches. Details on how to
select the right value for U1DLL and U1DLM can be found later in this chapter, see
Section
15.4.16.
All information provided in this document is subject to legal disclaimers.
Rev. 2 — 19 August 2010
Chapter 15: LPC17xx UART1
UM10360
© NXP B.V. 2010. All rights reserved.
NA
NA
Reset Value
undefined
Reset Value
NA
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