LPC1767FBD100,551 NXP Semiconductors, LPC1767FBD100,551 Datasheet - Page 760

• Manufacturer Part Number: LPC1767FBD100,551
• Description: IC ARM CORTEX MCU 512K 100-LQFP
• Manufacturer: NXP Semiconductors
• Series: LPC17xxr

Specifications of LPC1767FBD100,551

• Core Processor: ARM® Cortex-M3™
• Core Size: 32-Bit
• Speed: 100MHz
• Connectivity: Ethernet, I²C, IrDA, Microwire, SPI, SSI, UART/USART
• Peripherals: Brown-out Detect/Reset, DMA, I²S, Motor Control PWM, POR, PWM, WDT
• Number Of I /o: 70
• Program Memory Size: 512KB (512K x 8)
• Program Memory Type: FLASH
• Ram Size: 64K x 8
• Voltage - Supply (vcc/vdd): 2.4 V ~ 3.6 V
• Data Converters: A/D 8x12b, D/A 1x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 100-LQFP
• Processor Series: LPC17
• Core: ARM Cortex M3
• 3rd Party Development Tools: MDK-ARM, RL-ARM, ULINK2, MCB1760, MCB1760U, MCB1760UME
• For Use With: 622-1005 - USB IN-CIRCUIT PROG ARM7 LPC2K
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Details
• Other names: 568-4967; 935289808551

NXP Semiconductors
Table 644. NVIC register summary
[1]
UM10360
User manual
Address
0xE000E100 - 0xE000E10C
0XE000E180 - 0xE000E18C
0XE000E200 - 0xE000E20C
0XE000E280 - 0xE000E28C
0xE000E300 - 0xE000E30C
0xE000E400 - 0xE000E46C
0xE000EF00
Each array element corresponds to a single NVIC register, for example the element
34.4.2.1 The CMSIS mapping of the Cortex-M3 NVIC registers
34.4.2 Nested Vectored Interrupt Controller
This section describes the Nested Vectored Interrupt Controller (NVIC) and the registers it
uses. The NVIC supports:
The processor automatically stacks its state on exception entry and unstacks this state on
exception exit, with no instruction overhead. This provides low latency exception handling.
The hardware implementation of the NVIC registers is:
To improve software efficiency, the CMSIS simplifies the NVIC register presentation. In the
CMSIS:
•
•
•
•
•
•
•
•
•
Up to 112 interrupts. The number of interrupts implemented is device dependent.
A programmable priority level of 0 to 31 for each interrupt. A higher level corresponds
to a lower priority, so level 0 is the highest interrupt priority.
Level and pulse detection of interrupt signals.
Dynamic reprioritization of interrupts.
Grouping of priority values into group priority and subpriority fields.
Interrupt tail-chaining.
An external Non-maskable interrupt (NMI).
the Set-enable, Clear-enable, Set-pending, Clear-pending and Active Bit registers
map to arrays of 32-bit integers, so that:
– the array ISER[0] to ISER[3] corresponds to the registers ISER0 - ISER3
– the array ICER[0] to ICER[3] corresponds to the registers ICER0 - ICER3
– the array ISPR[0] to ISPR[3] corresponds to the registers ISPR0 - ISPR3
– the array ICPR[0] to ICPR[3] corresponds to the registers ICPR0 - ICPR3
– the array IABR[0] to IABR[3] corresponds to the registers IABR0 - IABR3.
the 8-bit fields of the Interrupt Priority Registers map to an array of 8-bit integers, so
that the array IP[0] to IP[112] corresponds to the registers IPR0 - IPR59, and the
array entry IP[n] holds the interrupt priority for interrupt n.
Name
ISER0 - ISER3
ICER0 - ICER3
ISPR0 - ISPR3
ICPR0 - ICPR3
IABR0 - IABR3
IPR0 - IPR27
STIR
All information provided in this document is subject to legal disclaimers.
Rev. 2 — 19 August 2010
Type
RW
RW
RW
RW
RO
RW
WO
Required
privilege
Privileged
Privileged
Privileged
Privileged
Privileged
Privileged
Configurable
Chapter 34: Appendix: Cortex-M3 user guide
[1]
ICER[1]
Reset
value
0x00000000
0x00000000
0x00000000
0x00000000
0x00000000
0x00000000
0x00000000
corresponds to the ICER1 register.
UM10360
© NXP B.V. 2010. All rights reserved.
Description
Table 646
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Table 648
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