LPC1767FBD100,551 NXP Semiconductors, LPC1767FBD100,551 Datasheet - Page 621

• Manufacturer Part Number: LPC1767FBD100,551
• Description: IC ARM CORTEX MCU 512K 100-LQFP
• Manufacturer: NXP Semiconductors
• Series: LPC17xxr

Specifications of LPC1767FBD100,551

• Core Processor: ARM® Cortex-M3™
• Core Size: 32-Bit
• Speed: 100MHz
• Connectivity: Ethernet, I²C, IrDA, Microwire, SPI, SSI, UART/USART
• Peripherals: Brown-out Detect/Reset, DMA, I²S, Motor Control PWM, POR, PWM, WDT
• Number Of I /o: 70
• Program Memory Size: 512KB (512K x 8)
• Program Memory Type: FLASH
• Ram Size: 64K x 8
• Voltage - Supply (vcc/vdd): 2.4 V ~ 3.6 V
• Data Converters: A/D 8x12b, D/A 1x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 100-LQFP
• Processor Series: LPC17
• Core: ARM Cortex M3
• 3rd Party Development Tools: MDK-ARM, RL-ARM, ULINK2, MCB1760, MCB1760U, MCB1760UME
• For Use With: 622-1005 - USB IN-CIRCUIT PROG ARM7 LPC2K
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Details
• Other names: 568-4967; 935289808551

NXP Semiconductors
32.6 Code Read Protection (CRP)
UM10360
User manual
Code Read Protection is a mechanism that allows user to enable different levels of
security in the system so that access to the on-chip flash and use of the ISP can be
restricted. When needed, CRP is invoked by programming a specific pattern in flash
location at 0x000002FC. IAP commands are not affected by the code read protection.
Important: Any CRP change becomes effective only after the device has gone
through a power cycle.
Table 568. Code Read Protection options
[1]
Name Pattern
CRP1 0x12345678
CRP2 0x87654321
CRP3 0x43218765
CRP is supported by all LPC17xx parts with the exception of part LPC1751 with
partID 0x2500 1110. Part LPC1751 with partID 0x2500 1118 supports all three CRP
levels (see Errata note).
programmed in
0x000002FC
All information provided in this document is subject to legal disclaimers.
Chapter 32: LPC17xx Flash memory interface and programming
Rev. 2 — 19 August 2010
Description
Access to chip via the JTAG pins is disabled. This mode allows partial
flash update using the following ISP commands and restrictions:
This mode is useful when CRP is required and flash field updates are
needed but all sectors can not be erased. The compare command is
disabled, so in the case of partial flash updates the secondary loader
should implement a checksum mechanism to verify the integrity of the
flash.
This is similar to CRP1 with the following additions:
disabled if a valid user code is present in flash sector 0.
This mode effectively disables ISP override using the P2.10 pin. It is
up to the user’s application to provide for flash updates by using IAP
calls or by invoking ISP with UART0.
Caution: If CRP3 is selected, no future factory testing can be
performed on the device.
This is similar to CRP2, but ISP entry by pulling P2.10 LOW is
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Write to RAM command can not access RAM below 0x10000200.
This is due to use of the RAM by the ISP code, see
Section
Read Memory command: disabled.
Copy RAM to Flash command: cannot write to Sector 0.
Go command: disabled.
Erase sector(s) command: can erase any individual sector except
sector 0 only, or can erase all sectors at once.
Compare command: disabled
Write to RAM command: disabled.
Copy RAM to Flash: disabled.
Erase command: only allows erase of all sectors.
32.3.2.7.
[1]
UM10360
© NXP B.V. 2010. All rights reserved.
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