LPC1767FBD100,551 NXP Semiconductors, LPC1767FBD100,551 Datasheet - Page 435
![IC ARM CORTEX MCU 512K 100-LQFP](/photos/6/65/66516/568-100-lqfp_sot407-1_sml.jpg)
LPC1767FBD100,551
Manufacturer Part Number
LPC1767FBD100,551
Description
IC ARM CORTEX MCU 512K 100-LQFP
Manufacturer
NXP Semiconductors
Series
LPC17xxr
Datasheets
1.LPC1767FBD100551.pdf
(2 pages)
2.LPC1767FBD100551.pdf
(840 pages)
3.LPC1767FBD100551.pdf
(65 pages)
Specifications of LPC1767FBD100,551
Core Processor
ARM® Cortex-M3™
Core Size
32-Bit
Speed
100MHz
Connectivity
Ethernet, I²C, IrDA, Microwire, SPI, SSI, UART/USART
Peripherals
Brown-out Detect/Reset, DMA, I²S, Motor Control PWM, POR, PWM, WDT
Number Of I /o
70
Program Memory Size
512KB (512K x 8)
Program Memory Type
FLASH
Ram Size
64K x 8
Voltage - Supply (vcc/vdd)
2.4 V ~ 3.6 V
Data Converters
A/D 8x12b, D/A 1x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
100-LQFP
Processor Series
LPC17
Core
ARM Cortex M3
3rd Party Development Tools
MDK-ARM, RL-ARM, ULINK2, MCB1760, MCB1760U, MCB1760UME
For Use With
622-1005 - USB IN-CIRCUIT PROG ARM7 LPC2K
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Lead Free Status / Rohs Status
Details
Other names
568-4967
935289808551
935289808551
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
LPC1767FBD100,551
Manufacturer:
NXP Semiconductors
Quantity:
10 000
- Current page: 435 of 840
- Download datasheet (6Mb)
NXP Semiconductors
UM10360
User manual
Fig 90. I
2
C serial interface block diagram
19.7.1 Input filters and output stages
SDA
SCL
status
bus
Input signals are synchronized with the internal clock, and spikes shorter than three
clocks are filtered out.
The output for I
OUTPUT
OUTPUT
FILTER
FILTER
STAGE
INPUT
STAGE
INPUT
DECODER
STATUS
2
All information provided in this document is subject to legal disclaimers.
C is a special pad designed to conform to the I
I2CnADDR0 to I2CnADDR3
ADDRESS REGISTERS
I2CnCONSET, I2CnCONCLR, I2CnSCLH, I2CnSCLL
MASK and COMPARE
Rev. 2 — 19 August 2010
ARBITRATION and
MONITOR MODE
SERIAL CLOCK
BIT COUNTER/
GENERATOR
I2CnMMCTRL
SYNC LOGIC
REGISTER
SCL DUTY CYLE REGISTERS
SHIFT REGISTER
CONTROL REGISTER and
STATUS REGISTER
I2CnDAT
I2CnSTAT
MATCHALL
I2CnMMCTRL[3]
I2CnMASK0 to I2CnMASK3
TIMING and
CONTROL
LOGIC
MASK REGISTERS
I2CnDATABUFFER
Chapter 19: LPC17xx I2C0/1/2
ACK
PCLK
interrupt
2
C specification.
16
8
8
8
UM10360
© NXP B.V. 2010. All rights reserved.
435 of 840
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