LPC1767FBD100,551 NXP Semiconductors, LPC1767FBD100,551 Datasheet - Page 699

• Manufacturer Part Number: LPC1767FBD100,551
• Description: IC ARM CORTEX MCU 512K 100-LQFP
• Manufacturer: NXP Semiconductors
• Series: LPC17xxr

Specifications of LPC1767FBD100,551

• Core Processor: ARM® Cortex-M3™
• Core Size: 32-Bit
• Speed: 100MHz
• Connectivity: Ethernet, I²C, IrDA, Microwire, SPI, SSI, UART/USART
• Peripherals: Brown-out Detect/Reset, DMA, I²S, Motor Control PWM, POR, PWM, WDT
• Number Of I /o: 70
• Program Memory Size: 512KB (512K x 8)
• Program Memory Type: FLASH
• Ram Size: 64K x 8
• Voltage - Supply (vcc/vdd): 2.4 V ~ 3.6 V
• Data Converters: A/D 8x12b, D/A 1x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 100-LQFP
• Processor Series: LPC17
• Core: ARM Cortex M3
• 3rd Party Development Tools: MDK-ARM, RL-ARM, ULINK2, MCB1760, MCB1760U, MCB1760UME
• For Use With: 622-1005 - USB IN-CIRCUIT PROG ARM7 LPC2K
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Details
• Other names: 568-4967; 935289808551

NXP Semiconductors
UM10360
User manual
34.2.7.1.3 Restrictions
34.2.7.1.4 Condition flags
34.2.7.1.5 Examples
If the returned result is different from the value to be saturated, it is called saturation. If
saturation occurs, the instruction sets the Q flag to 1 in the APSR. Otherwise, it leaves the
Q flag unchanged. To clear the Q flag to 0, you must use the MSR instruction, see
Section
To read the state of the Q flag, use the MRS instruction, see
Do not use SP and do not use PC.
These instructions do not affect the condition code flags.
If saturation occurs, these instructions set the Q flag to 1.
•
otherwise, the result returned is the same as the value to be saturated.
34.2.10.7.
SSAT
USATNE R0, #7, R5
All information provided in this document is subject to legal disclaimers.
R7, #16, R7, LSL #4 ; Logical shift left value in R7 by 4, then
Rev. 2 — 19 August 2010
; saturate it as a signed 16-bit value and
; write it back to R7
; Conditionally saturate value in R5 as an
; unsigned 7 bit value and write it to R0
Chapter 34: Appendix: Cortex-M3 user guide
Section
34.2.10.6.
UM10360
© NXP B.V. 2010. All rights reserved.
699 of 840