LPC1767FBD100,551 NXP Semiconductors, LPC1767FBD100,551 Datasheet - Page 5

• Manufacturer Part Number: LPC1767FBD100,551
• Description: IC ARM CORTEX MCU 512K 100-LQFP
• Manufacturer: NXP Semiconductors
• Series: LPC17xxr

Specifications of LPC1767FBD100,551

• Core Processor: ARM® Cortex-M3™
• Core Size: 32-Bit
• Speed: 100MHz
• Connectivity: Ethernet, I²C, IrDA, Microwire, SPI, SSI, UART/USART
• Peripherals: Brown-out Detect/Reset, DMA, I²S, Motor Control PWM, POR, PWM, WDT
• Number Of I /o: 70
• Program Memory Size: 512KB (512K x 8)
• Program Memory Type: FLASH
• Ram Size: 64K x 8
• Voltage - Supply (vcc/vdd): 2.4 V ~ 3.6 V
• Data Converters: A/D 8x12b, D/A 1x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 100-LQFP
• Processor Series: LPC17
• Core: ARM Cortex M3
• 3rd Party Development Tools: MDK-ARM, RL-ARM, ULINK2, MCB1760, MCB1760U, MCB1760UME
• For Use With: 622-1005 - USB IN-CIRCUIT PROG ARM7 LPC2K
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Details
• Other names: 568-4967; 935289808551

NXP Semiconductors
UM10360
User manual
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– I
Other peripherals:
– 70 (100 pin package) or 52 (80-pin package) General Purpose I/O (GPIO) pins with
– 12-bit Analog-to-Digital Converter (ADC) with input multiplexing among eight pins,
– 10-bit Digital-to-Analog Converter (DAC) with dedicated conversion timer and DMA
– Four general purpose timers/counters, with a total of eight capture inputs and ten
– One motor control PWM with support for three-phase motor control.
– Quadrature encoder interface that can monitor one external quadrature encoder.
– One standard PWM/timer block with external count input.
– Real-Time Clock (RTC) with a separate power domain. The RTC is clocked by a
– Watchdog Timer (WDT). The WDT can be clocked from the internal RC oscillator,
– Cortex-M3 system tick timer, including an external clock input option.
– Repetitive interrupt timer provides programmable and repeating timed interrupts.
Standard JTAG test/debug interface as well as Serial Wire Debug and Serial Wire
Trace Port options.
Emulation trace module supports real-time trace.
Four reduced power modes: Sleep, Deep-sleep, Power-down, and Deep
power-down.
Single 3.3 V power supply (2.4 V to 3.6 V). Temperature range of -40 °C to 85 °C.
Four external interrupt inputs configurable as edge/level sensitive. All pins on PORT0
and PORT2 can be used as edge sensitive interrupt sources.
Non-maskable Interrupt (NMI) input.
Clock output function that can reflect the main oscillator clock, IRC clock, RTC clock,
CPU clock, or the USB clock.
The Wakeup Interrupt Controller (WIC) allows the CPU to automatically wake up from
any priority interrupt that can occur while the clocks are stopped in deep sleep,
Power-down, and Deep power-down modes.
control. The I
3-wire data transmit and receive or 4-wire combined transmit and receive
connections, as well as master clock output.
configurable pull-up/down resistors, open drain mode, and repeater mode. All
GPIOs are located on an AHB bus for fast access, and support Cortex-M3
bit-banding. GPIOs can be accessed by the General Purpose DMA Controller. Any
pin of ports 0 and 2 can be used to generate an interrupt.
conversion rates up to 200 kHz, and multiple result registers. The 12-bit ADC can
be used with the GPDMA controller.
support.
compare outputs. Each timer block has an external count input. Specific timer
events can be selected to generate DMA requests.
dedicated RTC oscillator. The RTC block includes 20 bytes of battery-powered
backup registers, allowing system status to be stored when the rest of the chip is
powered off. Battery power can be supplied from a standard 3 V Lithium button
cell. The RTC will continue working when the battery voltage drops to as low as
2.1 V. An RTC interrupt can wake up the CPU from any reduced power mode.
the RTC oscillator, or the APB clock.
2
S (Inter-IC Sound) interface for digital audio input or output, with fractional rate
All information provided in this document is subject to legal disclaimers.
2
S interface can be used with the GPDMA. The I
Rev. 2 — 19 August 2010
Chapter 1: LPC17xx Introductory information
2
S interface supports
UM10360
© NXP B.V. 2010. All rights reserved.
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