LPC1767FBD100,551 NXP Semiconductors, LPC1767FBD100,551 Datasheet - Page 519
LPC1767FBD100,551
Manufacturer Part Number
LPC1767FBD100,551
Description
IC ARM CORTEX MCU 512K 100-LQFP
Manufacturer
NXP Semiconductors
Series
LPC17xxr
Datasheets
1.LPC1767FBD100551.pdf
(2 pages)
2.LPC1767FBD100551.pdf
(840 pages)
3.LPC1767FBD100551.pdf
(65 pages)
Specifications of LPC1767FBD100,551
Core Processor
ARM® Cortex-M3™
Core Size
32-Bit
Speed
100MHz
Connectivity
Ethernet, I²C, IrDA, Microwire, SPI, SSI, UART/USART
Peripherals
Brown-out Detect/Reset, DMA, I²S, Motor Control PWM, POR, PWM, WDT
Number Of I /o
70
Program Memory Size
512KB (512K x 8)
Program Memory Type
FLASH
Ram Size
64K x 8
Voltage - Supply (vcc/vdd)
2.4 V ~ 3.6 V
Data Converters
A/D 8x12b, D/A 1x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
100-LQFP
Processor Series
LPC17
Core
ARM Cortex M3
3rd Party Development Tools
MDK-ARM, RL-ARM, ULINK2, MCB1760, MCB1760U, MCB1760UME
For Use With
622-1005 - USB IN-CIRCUIT PROG ARM7 LPC2K
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Lead Free Status / Rohs Status
Details
Other names
568-4967
935289808551
935289808551
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
LPC1767FBD100,551
Manufacturer:
NXP Semiconductors
Quantity:
10 000
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NXP Semiconductors
Table 450: PWM Capture Control Register (PWM1CCR - address 0x4001 8028) bit description
Table 451: PWM Control Register (PWM1PCR - address 0x4001 804C) bit description
UM10360
User manual
6
8:7
9
10
11
12
13
Bit
3
4
5
31:6 -
Bit
1:0
2
3
4
5
Symbol
Capture on
CAPn.1rising
edge
Capture on
CAPn.1falling
edge
Interrupt on
CAPn.1 event
Symbol
Unused
PWMSEL2
PWMSEL3
PWMSEL4
PWMSEL5
PWMSEL6
-
PWMENA1
PWMENA2
PWMENA3
PWMENA4
PWMENA5
24.6.6 PWM Control Register (PWM1PCR - 0x4001 804C)
Value Description
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
Value Description
0
1
0
1
0
1
The PWM Control Register is used to enable and select the type of each PWM channel.
The function of each of the bits are shown in
Unused, always zero.
Selects double edge controlled mode for the PWM2 output.
Selects single edge controlled mode for PWM2.
Selects double edge controlled mode for the PWM3 output.
Selects single edge controlled mode for PWM3.
Selects double edge controlled mode for the PWM4 output.
Selects single edge controlled mode for PWM4.
Selects double edge controlled mode for the PWM5 output.
Selects single edge controlled mode for PWM5.
Selects double edge controlled mode for the PWM6 output.
Selects single edge controlled mode for PWM6.
Reserved, user software should not write ones to reserved bits. The value read from a
reserved bit is not defined.
The PWM1 output enabled.
The PWM1 output disabled.
The PWM2 output enabled.
The PWM2 output disabled.
The PWM3 output enabled.
The PWM3 output disabled.
The PWM4 output enabled.
The PWM4 output disabled.
The PWM5 output enabled.
The PWM5 output disabled.
This feature is disabled.
A synchronously sampled rising edge on the CAPn.1 input will cause CR1 to be
loaded with the contents of the TC.
This feature is disabled.
A synchronously sampled falling edge on CAPn.1 will cause CR1 to be loaded with
the contents of TC.
This feature is disabled.
A CR1 load due to a CAPn.1 event will generate an interrupt.
Reserved, user software should not write ones to reserved bits. The value read from
a reserved bit is not defined.
All information provided in this document is subject to legal disclaimers.
Rev. 2 — 19 August 2010
Chapter 24: LPC17xx Pulse Width Modulator (PWM)
Table
451.
UM10360
© NXP B.V. 2010. All rights reserved.
519 of 840
Reset
Value
0
0
0
NA
Reset
Value
NA
0
0
0
0
0
NA
0
0
0
0
0
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