LPC1767FBD100,551 NXP Semiconductors, LPC1767FBD100,551 Datasheet - Page 457
LPC1767FBD100,551
Manufacturer Part Number
LPC1767FBD100,551
Description
IC ARM CORTEX MCU 512K 100-LQFP
Manufacturer
NXP Semiconductors
Series
LPC17xxr
Datasheets
1.LPC1767FBD100551.pdf
(2 pages)
2.LPC1767FBD100551.pdf
(840 pages)
3.LPC1767FBD100551.pdf
(65 pages)
Specifications of LPC1767FBD100,551
Core Processor
ARM® Cortex-M3™
Core Size
32-Bit
Speed
100MHz
Connectivity
Ethernet, I²C, IrDA, Microwire, SPI, SSI, UART/USART
Peripherals
Brown-out Detect/Reset, DMA, I²S, Motor Control PWM, POR, PWM, WDT
Number Of I /o
70
Program Memory Size
512KB (512K x 8)
Program Memory Type
FLASH
Ram Size
64K x 8
Voltage - Supply (vcc/vdd)
2.4 V ~ 3.6 V
Data Converters
A/D 8x12b, D/A 1x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
100-LQFP
Processor Series
LPC17
Core
ARM Cortex M3
3rd Party Development Tools
MDK-ARM, RL-ARM, ULINK2, MCB1760, MCB1760U, MCB1760UME
For Use With
622-1005 - USB IN-CIRCUIT PROG ARM7 LPC2K
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Lead Free Status / Rohs Status
Details
Other names
568-4967
935289808551
935289808551
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
LPC1767FBD100,551
Manufacturer:
NXP Semiconductors
Quantity:
10 000
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NXP Semiconductors
Table 398. Master Transmitter mode
UM10360
User manual
I2CSTAT
Status
Code
0x08
0x10
0x18
0x20
0x28
0x30
0x38
Status of the
I
hardware
A START condition
has been transmitted.
A repeated START
condition has been
transmitted.
SLA+W has been
transmitted; ACK has
been received.
SLA+W has been
transmitted; NOT
ACK has been
received.
Data byte in I2DAT
has been transmitted;
ACK has been
received.
Data byte in I2DAT
has been transmitted;
NOT ACK has been
received.
Arbitration lost in
SLA+R/W or Data
bytes.
2
C-bus and
19.9.5 Detailed state tables
The following tables show detailed state information for the four I
Application software response
To/From I2DAT
Load SLA+W; clear
STA
Load SLA+W or
Load SLA+R; Clear
STA
Load data byte or
No I2DAT action or
No I2DAT action or
No I2DAT action
Load data byte or
No I2DAT action or
No I2DAT action or
No I2DAT action
Load data byte or
No I2DAT action or
No I2DAT action or
No I2DAT action
Load data byte or
No I2DAT action or
No I2DAT action or
No I2DAT action
No I2DAT action or
No I2DAT action
All information provided in this document is subject to legal disclaimers.
Rev. 2 — 19 August 2010
To I2CON
STA STO SI
X
X
X
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
0
0
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
AA
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
Next action taken by I
SLA+W will be transmitted; ACK bit will
be received.
As above.
SLA+W will be transmitted; the I
will be switched to MST/REC mode.
Data byte will be transmitted; ACK bit will
be received.
Repeated START will be transmitted.
STOP condition will be transmitted; STO
flag will be reset.
STOP condition followed by a START
condition will be transmitted; STO flag will
be reset.
Data byte will be transmitted; ACK bit will
be received.
Repeated START will be transmitted.
STOP condition will be transmitted; STO
flag will be reset.
STOP condition followed by a START
condition will be transmitted; STO flag will
be reset.
Data byte will be transmitted; ACK bit will
be received.
Repeated START will be transmitted.
STOP condition will be transmitted; STO
flag will be reset.
STOP condition followed by a START
condition will be transmitted; STO flag will
be reset.
Data byte will be transmitted; ACK bit will
be received.
Repeated START will be transmitted.
STOP condition will be transmitted; STO
flag will be reset.
STOP condition followed by a START
condition will be transmitted; STO flag will
be reset.
I
slave will be entered.
A START condition will be transmitted
when the bus becomes free.
2
C-bus will be released; not addressed
Chapter 19: LPC17xx I2C0/1/2
2
C operating modes.
UM10360
© NXP B.V. 2010. All rights reserved.
2
C hardware
2
457 of 840
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