LPC1767FBD100,551 NXP Semiconductors, LPC1767FBD100,551 Datasheet - Page 493

• Manufacturer Part Number: LPC1767FBD100,551
• Description: IC ARM CORTEX MCU 512K 100-LQFP
• Manufacturer: NXP Semiconductors
• Series: LPC17xxr

Specifications of LPC1767FBD100,551

• Core Processor: ARM® Cortex-M3™
• Core Size: 32-Bit
• Speed: 100MHz
• Connectivity: Ethernet, I²C, IrDA, Microwire, SPI, SSI, UART/USART
• Peripherals: Brown-out Detect/Reset, DMA, I²S, Motor Control PWM, POR, PWM, WDT
• Number Of I /o: 70
• Program Memory Size: 512KB (512K x 8)
• Program Memory Type: FLASH
• Ram Size: 64K x 8
• Voltage - Supply (vcc/vdd): 2.4 V ~ 3.6 V
• Data Converters: A/D 8x12b, D/A 1x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 100-LQFP
• Processor Series: LPC17
• Core: ARM Cortex M3
• 3rd Party Development Tools: MDK-ARM, RL-ARM, ULINK2, MCB1760, MCB1760U, MCB1760UME
• For Use With: 622-1005 - USB IN-CIRCUIT PROG ARM7 LPC2K
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Details
• Other names: 568-4967; 935289808551

NXP Semiconductors
Table 425. TIMER/COUNTER0-3 register map
Table 426. Interrupt Register (T[0/1/2/3]IR - addresses 0x4000 4000, 0x4000 8000, 0x4009 0000, 0x4009 4000) bit
UM10360
User manual
Generic
Name
CR0
CR1
EMR
CTCR
Bit
0
1
2
3
4
5
31:6
Symbol
MR0 Interrupt
MR1 Interrupt
MR2 Interrupt
MR3 Interrupt
CR0 Interrupt
CR1 Interrupt
-
Description
Capture Register 0. CR0 is loaded with the value of TC when there
is an event on the CAPn.0(CAP0.0 or CAP1.0 respectively) input.
Capture Register 1. See CR0 description.
External Match Register. The EMR controls the external match pins
MATn.0-3 (MAT0.0-3 and MAT1.0-3 respectively).
Count Control Register. The CTCR selects between Timer and
Counter mode, and in Counter mode selects the signal and edge(s)
for counting.
description
21.6.1 Interrupt Register (T[0/1/2/3]IR - 0x4000 4000, 0x4000 8000,
21.6.2 Timer Control Register (T[0/1/2/3]CR - 0x4000 4004, 0x4000 8004,
Description
Interrupt flag for match channel 0.
Interrupt flag for match channel 1.
Interrupt flag for match channel 2.
Interrupt flag for match channel 3.
Interrupt flag for capture channel 0 event.
Interrupt flag for capture channel 1 event.
Reserved
[1]
0x4009 0000, 0x4009 4000)
The Interrupt Register consists of 4 bits for the match interrupts and 4 bits for the capture
interrupts. If an interrupt is generated then the corresponding bit in the IR will be high.
Otherwise, the bit will be low. Writing a logic one to the corresponding IR bit will reset the
interrupt. Writing a zero has no effect. The act of clearing an interrupt for a timer match
also clears any corresponding DMA request.
0x4009 0004, 0x4009 4004)
The Timer Control Register (TCR) is used to control the operation of the Timer/Counter.
Reset Value reflects the data stored in used bits only. It does not include reserved bits content.
All information provided in this document is subject to legal disclaimers.
Rev. 2 — 19 August 2010
Access Reset
RO
RO
R/W
R/W
Chapter 21: LPC17xx Timer 0/1/2/3
Value
0
0
0
0
[1]
TIMERn Register/
Name & Address
T0CR0 - 0x4000 402C
T1CR0 - 0x4000 802C
T2CR0 - 0x4009 002C
T3CR0 - 0x4009 402C
T0CR1 - 0x4000 4030
T1CR1 - 0x4000 8030
T2CR1 - 0x4009 0030
T3CR1 - 0x4009 4030
T0EMR - 0x4000 403C
T1EMR - 0x4000 803C
T2EMR - 0x4009 003C
T3EMR - 0x4009 403C
T0CTCR - 0x4000 4070
T1CTCR - 0x4000 8070
T2CTCR - 0x4009 0070
T3CTCR - 0x4009 4070
UM10360
© NXP B.V. 2010. All rights reserved.
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Reset
Value
0
0
0
0
0
0
-