LPC1767FBD100,551 NXP Semiconductors, LPC1767FBD100,551 Datasheet - Page 120
LPC1767FBD100,551
Manufacturer Part Number
LPC1767FBD100,551
Description
IC ARM CORTEX MCU 512K 100-LQFP
Manufacturer
NXP Semiconductors
Series
LPC17xxr
Datasheets
1.LPC1767FBD100551.pdf
(2 pages)
2.LPC1767FBD100551.pdf
(840 pages)
3.LPC1767FBD100551.pdf
(65 pages)
Specifications of LPC1767FBD100,551
Core Processor
ARM® Cortex-M3™
Core Size
32-Bit
Speed
100MHz
Connectivity
Ethernet, I²C, IrDA, Microwire, SPI, SSI, UART/USART
Peripherals
Brown-out Detect/Reset, DMA, I²S, Motor Control PWM, POR, PWM, WDT
Number Of I /o
70
Program Memory Size
512KB (512K x 8)
Program Memory Type
FLASH
Ram Size
64K x 8
Voltage - Supply (vcc/vdd)
2.4 V ~ 3.6 V
Data Converters
A/D 8x12b, D/A 1x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
100-LQFP
Processor Series
LPC17
Core
ARM Cortex M3
3rd Party Development Tools
MDK-ARM, RL-ARM, ULINK2, MCB1760, MCB1760U, MCB1760UME
For Use With
622-1005 - USB IN-CIRCUIT PROG ARM7 LPC2K
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Lead Free Status / Rohs Status
Details
Other names
568-4967
935289808551
935289808551
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
LPC1767FBD100,551
Manufacturer:
NXP Semiconductors
Quantity:
10 000
- Current page: 120 of 840
- Download datasheet (6Mb)
9.1 Basic configuration
9.2 Features
UM10360
User manual
9.2.1 Digital I/O ports
9.2.2 Interrupt generating digital ports
GPIOs are configured using the following registers:
1. Power: always enabled.
2. Pins: See
3. Wake-up: GPIO ports 0 and 2 can be used for wake-up if needed, see
4. Interrupts: Enable GPIO interrupts in IO0/2IntEnR
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UM10360
Chapter 9: LPC17xx General Purpose Input/Output (GPIO)
Rev. 2 — 19 August 2010
(Table
Enable register.
Accelerated GPIO functions:
– GPIO registers are located on a peripheral AHB bus for fast I/O timing.
– Mask registers allow treating sets of port bits as a group, leaving other bits
– All GPIO registers are byte, half-word, and word addressable.
– Entire port value can be written in one instruction.
– GPIO registers are accessible by the GPDMA.
Bit-level set and clear registers allow a single instruction set or clear of any number of
bits in one port.
All GPIO registers support Cortex-M3 bit-banding.
GPIO registers are accessible by the GPDMA controller to allow DMA of data to or
from GPIOs, synchronized to any DMA request.
Direction control of individual port bits.
All I/Os default to input with pullup after reset.
Port 0 and Port 2 can provide a single interrupt for any combination of port pins.
Each port pin can be programmed to generate an interrupt on a rising edge, a falling
edge, or both.
Edge detection is asynchronous, so it may operate when clocks are not present, such
as during Power-down mode. With this feature, level triggered interrupts are not
needed.
Each enabled interrupt contributes to a wake-up signal that can be used to bring the
part out of Power-down mode.
unchanged.
116). Interrupts are enabled in the NVIC using the appropriate Interrupt Set
Section 8.3
All information provided in this document is subject to legal disclaimers.
Rev. 2 — 19 August 2010
for GPIO pins and their modes.
(Table
114) or IO0/2IntEnF
© NXP B.V. 2010. All rights reserved.
(Section
User manual
120 of 840
4.8.8).
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