LPC1767FBD100,551 NXP Semiconductors, LPC1767FBD100,551 Datasheet - Page 300

• Manufacturer Part Number: LPC1767FBD100,551
• Description: IC ARM CORTEX MCU 512K 100-LQFP
• Manufacturer: NXP Semiconductors
• Series: LPC17xxr

Specifications of LPC1767FBD100,551

• Core Processor: ARM® Cortex-M3™
• Core Size: 32-Bit
• Speed: 100MHz
• Connectivity: Ethernet, I²C, IrDA, Microwire, SPI, SSI, UART/USART
• Peripherals: Brown-out Detect/Reset, DMA, I²S, Motor Control PWM, POR, PWM, WDT
• Number Of I /o: 70
• Program Memory Size: 512KB (512K x 8)
• Program Memory Type: FLASH
• Ram Size: 64K x 8
• Voltage - Supply (vcc/vdd): 2.4 V ~ 3.6 V
• Data Converters: A/D 8x12b, D/A 1x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 100-LQFP
• Processor Series: LPC17
• Core: ARM Cortex M3
• 3rd Party Development Tools: MDK-ARM, RL-ARM, ULINK2, MCB1760, MCB1760U, MCB1760UME
• For Use With: 622-1005 - USB IN-CIRCUIT PROG ARM7 LPC2K
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Details
• Other names: 568-4967; 935289808551

NXP Semiconductors
Table 270. UART0/2/3 Register Map
[1]
UM10360
User manual
Generic Name
RBR (DLAB =0)
THR (DLAB =0)
DLL (DLAB =1)
DLM (DLAB =1)
IER (DLAB =0)
IIR
FCR
LCR
LSR
SCR
ACR
ICR
FDR
TER
Reset Value reflects the data stored in used bits only. It does not include reserved bits content.
Description
Receiver Buffer Register. Contains the next received
character to be read.
Transmit Holding Register. The next character to be
transmitted is written here.
Divisor Latch LSB. Least significant byte of the baud
rate divisor value. The full divisor is used to generate a
baud rate from the fractional rate divider.
Divisor Latch MSB. Most significant byte of the baud
rate divisor value. The full divisor is used to generate a
baud rate from the fractional rate divider.
Interrupt Enable Register. Contains individual interrupt
enable bits for the 7 potential UART interrupts.
Interrupt ID Register. Identifies which interrupt(s) are
pending.
FIFO Control Register. Controls UART FIFO usage and
modes.
Line Control Register. Contains controls for frame
formatting and break generation.
Line Status Register. Contains flags for transmit and
receive status, including line errors.
Scratch Pad Register. 8-bit temporary storage for
software.
Auto-baud Control Register. Contains controls for the
auto-baud feature.
IrDA Control Register.
IrDA mode.
Fractional Divider Register. Generates a clock input for
the baud rate divider.
Transmit Enable Register. Turns off UART transmitter
for use with software flow control.
All information provided in this document is subject to legal disclaimers.
Enables and configures the
Rev. 2 — 19 August 2010
Access Reset
RO
WO
R/W
R/W
R/W
RO
WO
R/W
RO
R/W
R/W
R/W
R/W
R/W
Chapter 14: LPC17xx UART0/2/3
value
NA
NA
0x01
0x00
0x00
0x01
0x00
0x00
0x60
0x00
0x00
0x00
0x10
0x80
[1]
UARTn Register
Name & Address
U0RBR - 0x4000 C000
U2RBR - 0x4009 8000
U3RBR - 0x4009 C000
U0THR - 0x4000 C000
U2THR - 0x4009 8000
U3THR - 0x4009 C000
U0DLL - 0x4000 C000
U2DLL - 0x4009 8000
U3DLL - 0x4009 C000
U0DLM - 0x4000 C004
U2DLM - 0x4009 8004
U3DLM - 0x4009 C004
U0IER - 0x4000 C004
U2IER - 0x4009 8004
U3IER - 0x4009 C004
U0IIR - 0x4000 C008
U2IIR - 0x4009 8008
U3IIR - 0x4009 C008
U0FCR - 0x4000 C008
U2FCR - 0x4009 8008
U3FCR - 0x4009 C008
U0LCR - 0x4000 C00C
U2LCR - 0x4009 800C
U3LCR - 0x4009 C00C
U0LSR - 0x4000 C014
U2LSR - 0x4009 8014
U3LSR - 0x4009 C014
U0SCR - 0x4000 C01C
U2SCR - 0x4009 801C
U3SCR - 0x4009 C01C
U0ACR - 0x4000 C020
U2ACR - 0x4009 8020
U3ACR - 0x4009 C020
U0ICR - 0x4000 C024
U2ICR - 0x4009 8024
U3ICR - 0x4009 C024
U0FDR - 0x4000 C028
U2FDR - 0x4009 8028
U3FDR - 0x4009 C028
U0TER - 0x4000 C030
U2TER - 0x4009 8030
U3TER - 0x4009 C030
UM10360
© NXP B.V. 2010. All rights reserved.
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