LPC1767FBD100,551 NXP Semiconductors, LPC1767FBD100,551 Datasheet - Page 502
LPC1767FBD100,551
Manufacturer Part Number
LPC1767FBD100,551
Description
IC ARM CORTEX MCU 512K 100-LQFP
Manufacturer
NXP Semiconductors
Series
LPC17xxr
Datasheets
1.LPC1767FBD100551.pdf
(2 pages)
2.LPC1767FBD100551.pdf
(840 pages)
3.LPC1767FBD100551.pdf
(65 pages)
Specifications of LPC1767FBD100,551
Core Processor
ARM® Cortex-M3™
Core Size
32-Bit
Speed
100MHz
Connectivity
Ethernet, I²C, IrDA, Microwire, SPI, SSI, UART/USART
Peripherals
Brown-out Detect/Reset, DMA, I²S, Motor Control PWM, POR, PWM, WDT
Number Of I /o
70
Program Memory Size
512KB (512K x 8)
Program Memory Type
FLASH
Ram Size
64K x 8
Voltage - Supply (vcc/vdd)
2.4 V ~ 3.6 V
Data Converters
A/D 8x12b, D/A 1x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
100-LQFP
Processor Series
LPC17
Core
ARM Cortex M3
3rd Party Development Tools
MDK-ARM, RL-ARM, ULINK2, MCB1760, MCB1760U, MCB1760UME
For Use With
622-1005 - USB IN-CIRCUIT PROG ARM7 LPC2K
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Lead Free Status / Rohs Status
Details
Other names
568-4967
935289808551
935289808551
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
LPC1767FBD100,551
Manufacturer:
NXP Semiconductors
Quantity:
10 000
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NXP Semiconductors
Table 436. RI Control register (RICTRL - address 0x400B 0008) bit description
Table 437. RI Counter register (RICOUNTER - address 0x400B 000C) bit description
22.4 RI timer operation
UM10360
User manual
Bit
0
1
2
3
31:4
Bit
31:0
RITINT
RITENCLR
RITENBR
RITEN
-
Symbol
Symbol
RICOUNTER
22.3.3 RI Control register (RICTRL - 0x400B 0008)
22.3.4 RI Counter register (RICOUNTER - 0x400B 000C)
Value
1
0
1
0
1
0
1
0
-
Description
32-bit up counter. Counts continuously unless RITEN bit in RICTRL register is cleared or
debug mode is entered (if enabled by the RITNEBR bit in RICTRL). Can be loaded to any
value in software.
Following reset, the counter begins counting up from 00000000h. Whenever the counter
value equals the value programmed into the RICOMPVAL register the interrupt flag will be
set. Any bit or combination of bits can be removed from this comparison (i.e. forced to
compare) by writing a ‘1’ to the corresponding bit(s) in the RIMASK register. If the
enable_clr bit is low (default state), a valid comparison ONLY causes the interrupt flag to
be set. It has no effect on the count sequence. Counting continues as usual. When the
counter reaches FFFFFFFFh it rolls-over to 00000000h on the next clock and continues
counting. If the enable_clr bit is set to ‘1’ a valid comparison will also cause the counter to
be reset to zero. Counting will resume from there on the next clock edge.
Description
Interrupt flag
This bit is set to 1 by hardware whenever the counter value equals the masked
compare value specified by the contents of RICOMPVAL and RIMASK registers.
Writing a 1 to this bit will clear it to 0. Writing a 0 has no effect.
The counter value does not equal the masked compare value.
Timer enable clear
The timer will be cleared to 0 whenever the counter value equals the masked compare
value specified by the contents of RICOMPVAL and RIMASK registers. This will occur
on the same clock that sets the interrupt flag.
The timer will not be cleared to 0.
Timer enable for debug
The timer is halted when the processor is halted for debugging.
Debug has no effect on the timer operation.
Timer enable.
Timer enabled.
Remark: This can be overruled by a debug halt if enabled in bit 2.
Timer disabled.
Reserved, user software should not write ones to reserved bits. The value read from a
reserved bit is not defined.
All information provided in this document is subject to legal disclaimers.
Rev. 2 — 19 August 2010
Chapter 22: LPC17xx Repetitive Interrupt Timer (RIT)
UM10360
© NXP B.V. 2010. All rights reserved.
502 of 840
Reset
value
0
0
1
1
NA
Reset
value
0
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