LPC1767FBD100,551 NXP Semiconductors, LPC1767FBD100,551 Datasheet - Page 499

• Manufacturer Part Number: LPC1767FBD100,551
• Description: IC ARM CORTEX MCU 512K 100-LQFP
• Manufacturer: NXP Semiconductors
• Series: LPC17xxr

Specifications of LPC1767FBD100,551

• Core Processor: ARM® Cortex-M3™
• Core Size: 32-Bit
• Speed: 100MHz
• Connectivity: Ethernet, I²C, IrDA, Microwire, SPI, SSI, UART/USART
• Peripherals: Brown-out Detect/Reset, DMA, I²S, Motor Control PWM, POR, PWM, WDT
• Number Of I /o: 70
• Program Memory Size: 512KB (512K x 8)
• Program Memory Type: FLASH
• Ram Size: 64K x 8
• Voltage - Supply (vcc/vdd): 2.4 V ~ 3.6 V
• Data Converters: A/D 8x12b, D/A 1x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 100-LQFP
• Processor Series: LPC17
• Core: ARM Cortex M3
• 3rd Party Development Tools: MDK-ARM, RL-ARM, ULINK2, MCB1760, MCB1760U, MCB1760UME
• For Use With: 622-1005 - USB IN-CIRCUIT PROG ARM7 LPC2K
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Details
• Other names: 568-4967; 935289808551

NXP Semiconductors
21.7 Example timer operation
UM10360
User manual
Fig 114. A timer cycle in which PR=2, MRx=6, and both interrupt and reset on match are enabled.
Fig 115. A timer Cycle in Which PR=2, MRx=6, and both interrupt and stop on match are enabled
prescale counter
timer counter
(counter enable)
timer counter
prescale
interrupt
counter
counter
PCLK
timer
reset
interrupt
TCR[0]
PCLK
When a timer is initially set up to generate a DMA request, the request may already be
asserted before a match condition occurs. An initial DMA request may be avoided by
having software write a one to the interrupt flag location, as if clearing a timer interrupt.
See
the GPDMA controller.
Remark: Because timer DMA requests are generated whenever the timer value is equal
to the related Match Register value, DMA requests are always generated when the timer
is running, unless the Match Register value is higher than the upper count limit of the
timer. It is important not to select and enable timer DMA requests in the GPDMA block
unless the timer is correctly configured to generate valid DMA requests.
Figure 114
match. The prescaler is set to 2 and the match register set to 6. At the end of the timer
cycle where the match occurs, the timer count is reset. This gives a full length cycle to the
match value. The interrupt indicating that a match occurred is generated in the next clock
after the timer reached the match value.
Figure 115
prescaler is again set to 2 and the match register set to 6. In the next clock after the timer
reaches the match value, the timer enable bit in TCR is cleared, and the interrupt
indicating that a match occurred is generated.
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shows a timer configured to reset the count and generate an interrupt on
shows a timer configured to stop and generate an interrupt on match. The
21.6.1. A DMA request will be cleared automatically when it is acted upon by
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Chapter 21: LPC17xx Timer 0/1/2/3
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