LPC1767FBD100,551 NXP Semiconductors, LPC1767FBD100,551 Datasheet - Page 324

• Manufacturer Part Number: LPC1767FBD100,551
• Description: IC ARM CORTEX MCU 512K 100-LQFP
• Manufacturer: NXP Semiconductors
• Series: LPC17xxr

Specifications of LPC1767FBD100,551

• Core Processor: ARM® Cortex-M3™
• Core Size: 32-Bit
• Speed: 100MHz
• Connectivity: Ethernet, I²C, IrDA, Microwire, SPI, SSI, UART/USART
• Peripherals: Brown-out Detect/Reset, DMA, I²S, Motor Control PWM, POR, PWM, WDT
• Number Of I /o: 70
• Program Memory Size: 512KB (512K x 8)
• Program Memory Type: FLASH
• Ram Size: 64K x 8
• Voltage - Supply (vcc/vdd): 2.4 V ~ 3.6 V
• Data Converters: A/D 8x12b, D/A 1x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 100-LQFP
• Processor Series: LPC17
• Core: ARM Cortex M3
• 3rd Party Development Tools: MDK-ARM, RL-ARM, ULINK2, MCB1760, MCB1760U, MCB1760UME
• For Use With: 622-1005 - USB IN-CIRCUIT PROG ARM7 LPC2K
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Details
• Other names: 568-4967; 935289808551

NXP Semiconductors
Table 296: UART1 Interrupt Handling
UM10360
User manual
U1IIR[3:0]
value
0001
0110
0100
1100
0010
0000
[1]
Priority Interrupt
-
Highest RX Line
Second RX Data
Second Character
Third
Fourth
Type
None
Status /
Error
Available
Time-out
indication
THRE
Modem
Status
interrupt handler routine can determine the cause of the interrupt and how to clear the
active interrupt. The U1IIR must be read in order to clear the interrupt prior to exiting the
Interrupt Service Routine.
The UART1 RLS interrupt (U1IIR[3:1] = 011) is the highest priority interrupt and is set
whenever any one of four error conditions occur on the UART1RX input: overrun error
(OE), parity error (PE), framing error (FE) and break interrupt (BI). The UART1 Rx error
condition that set the interrupt can be observed via U1LSR[4:1]. The interrupt is cleared
upon an U1LSR read.
The UART1 RDA interrupt (U1IIR[3:1] = 010) shares the second level priority with the CTI
interrupt (U1IIR[3:1] = 110). The RDA is activated when the UART1 Rx FIFO reaches the
trigger level defined in U1FCR7:6 and is reset when the UART1 Rx FIFO depth falls below
the trigger level. When the RDA interrupt goes active, the CPU can read a block of data
defined by the trigger level.
The CTI interrupt (U1IIR[3:1] = 110) is a second level interrupt and is set when the UART1
Rx FIFO contains at least one character and no UART1 Rx FIFO activity has occurred in
3.5 to 4.5 character times. Any UART1 Rx FIFO activity (read or write of UART1 RSR) will
clear the interrupt. This interrupt is intended to flush the UART1 RBR after a message has
been received that is not a multiple of the trigger level size. For example, if a peripheral
wished to send a 105 character message and the trigger level was 10 characters, the
CPU would receive 10 RDA interrupts resulting in the transfer of 100 characters and 1 to 5
CTI interrupts (depending on the service routine) resulting in the transfer of the remaining
5 characters.
[1]
[2]
[3]
[4]
Values "0000", “0011”, “0101”, “0111”, “1000”, “1001”, “1010”, “1011”,”1101”,”1110”,”1111” are reserved.
For details see
For details see
For details see
Section 15.4.2 “UART1 Transmitter Holding Register (U1THR - 0x4001 0000 when DLAB = 0)”
Interrupt Source
None
OE
Rx data available or trigger level reached in FIFO
(U1FCR0=1)
Minimum of one character in the RX FIFO and no
character input or removed during a time period depending
on how many characters are in FIFO and what the trigger
level is set at (3.5 to 4.5 character times).
The exact time will be:
[(word length) × 7 - 2] × 8 + [(trigger level - number of
characters) × 8 + 1] RCLKs
THRE
CTS or DSR or RI or DCD
[2]
or PE
[2]
All information provided in this document is subject to legal disclaimers.
Section 15.4.10 “UART1 Line Status Register (U1LSR - 0x4001 0014)”
Section 15.4.1 “UART1 Receiver Buffer Register (U1RBR - 0x4001 0000, when DLAB = 0)”
Section 15.4.5 “UART1 Interrupt Identification Register (U1IIR - 0x4001 0008)”
[2]
or FE
Rev. 2 — 19 August 2010
[2]
or BI
[2]
Chapter 15: LPC17xx UART1
Interrupt Reset
-
U1LSR Read
U1RBR Read
FIFO drops below trigger level
U1RBR Read
U1IIR Read
interrupt) or THR write
MSR Read
UM10360
© NXP B.V. 2010. All rights reserved.
[4]
[2]
[3]
[3]
(if source of
or UART1
and
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