LPC1767FBD100,551 NXP Semiconductors, LPC1767FBD100,551 Datasheet - Page 90

• Manufacturer Part Number: LPC1767FBD100,551
• Description: IC ARM CORTEX MCU 512K 100-LQFP
• Manufacturer: NXP Semiconductors
• Series: LPC17xxr

Specifications of LPC1767FBD100,551

• Core Processor: ARM® Cortex-M3™
• Core Size: 32-Bit
• Speed: 100MHz
• Connectivity: Ethernet, I²C, IrDA, Microwire, SPI, SSI, UART/USART
• Peripherals: Brown-out Detect/Reset, DMA, I²S, Motor Control PWM, POR, PWM, WDT
• Number Of I /o: 70
• Program Memory Size: 512KB (512K x 8)
• Program Memory Type: FLASH
• Ram Size: 64K x 8
• Voltage - Supply (vcc/vdd): 2.4 V ~ 3.6 V
• Data Converters: A/D 8x12b, D/A 1x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 100-LQFP
• Processor Series: LPC17
• Core: ARM Cortex M3
• 3rd Party Development Tools: MDK-ARM, RL-ARM, ULINK2, MCB1760, MCB1760U, MCB1760UME
• For Use With: 622-1005 - USB IN-CIRCUIT PROG ARM7 LPC2K
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Details
• Other names: 568-4967; 935289808551

NXP Semiconductors
Table 71.
UM10360
User manual
Bit
8:0
31:9
Name
INTID
-
Software Trigger Interrupt Register (STIR - 0xE000 EF00)
6.5.20 Software Trigger Interrupt Register (STIR - 0xE000 EF00)
The STIR register provides an alternate way for software to generate an interrupt, in
addition to using the ISPR registers. This mechanism can only be used to generate
peripheral interrupts, not system exceptions.
By default, only privileged software can write to the STIR register. Unprivileged software
can be given this ability if privileged software sets the USERSETMPEND bit in the CCR
register (see
Function
Writing a value to this field generates an interrupt for the specified the interrupt number (see
Table
Reserved, user software should not write ones to reserved bits. The value read from a reserved
bit is not defined.
50). The range allowed for the LPC17xx is 0 to 111.
Section
All information provided in this document is subject to legal disclaimers.
Chapter 6: LPC17xx Nested Vectored Interrupt Controller (NVIC)
34.4.3.8).
Rev. 2 — 19 August 2010
UM10360
© NXP B.V. 2010. All rights reserved.
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