LPC1767FBD100,551 NXP Semiconductors, LPC1767FBD100,551 Datasheet - Page 656
![IC ARM CORTEX MCU 512K 100-LQFP](/photos/6/65/66516/568-100-lqfp_sot407-1_sml.jpg)
LPC1767FBD100,551
Manufacturer Part Number
LPC1767FBD100,551
Description
IC ARM CORTEX MCU 512K 100-LQFP
Manufacturer
NXP Semiconductors
Series
LPC17xxr
Datasheets
1.LPC1767FBD100551.pdf
(2 pages)
2.LPC1767FBD100551.pdf
(840 pages)
3.LPC1767FBD100551.pdf
(65 pages)
Specifications of LPC1767FBD100,551
Core Processor
ARM® Cortex-M3™
Core Size
32-Bit
Speed
100MHz
Connectivity
Ethernet, I²C, IrDA, Microwire, SPI, SSI, UART/USART
Peripherals
Brown-out Detect/Reset, DMA, I²S, Motor Control PWM, POR, PWM, WDT
Number Of I /o
70
Program Memory Size
512KB (512K x 8)
Program Memory Type
FLASH
Ram Size
64K x 8
Voltage - Supply (vcc/vdd)
2.4 V ~ 3.6 V
Data Converters
A/D 8x12b, D/A 1x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
100-LQFP
Processor Series
LPC17
Core
ARM Cortex M3
3rd Party Development Tools
MDK-ARM, RL-ARM, ULINK2, MCB1760, MCB1760U, MCB1760UME
For Use With
622-1005 - USB IN-CIRCUIT PROG ARM7 LPC2K
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Lead Free Status / Rohs Status
Details
Other names
568-4967
935289808551
935289808551
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
LPC1767FBD100,551
Manufacturer:
NXP Semiconductors
Quantity:
10 000
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NXP Semiconductors
UM10360
User manual
34.2.3.6 PC-relative expressions
34.2.3.7 Conditional execution
Unaligned accesses are usually slower than aligned accesses. In addition, some memory
regions might not support unaligned accesses. Therefore, ARM recommends that
programmers ensure that accesses are aligned. To avoid accidental generation of
unaligned accesses, use the UNALIGN_TRP bit in the Configuration and Control Register
to trap all unaligned accesses, see
A PC-relative expression or label is a symbol that represents the address of an instruction
or literal data. It is represented in the instruction as the PC value plus or minus a numeric
offset. The assembler calculates the required offset from the label and the address of the
current instruction. If the offset is too big, the assembler produces an error.
Note
Most data processing instructions can optionally update the condition flags in the
Application Program Status Register (APSR) according to the result of the operation,
see
some only update a subset. If a flag is not updated, the original value is preserved. See
the instruction descriptions for the flags they affect.
You can execute an instruction conditionally, based on the condition flags set in another
instruction, either:
Conditional execution is available by using conditional branches or by adding condition
code suffixes to instructions. See
to make them conditional instructions. The condition code suffix enables the processor to
test a condition based on the flags. If the condition test of a conditional instruction fails,
the instruction:
Conditional instructions, except for conditional branches, must be inside an If-Then
instruction block. See
the IT instruction. Depending on the vendor, the assembler might automatically insert an
IT instruction if you have conditional instructions outside the IT block.
•
•
•
•
•
•
•
•
•
For B, BL, CBNZ, and CBZ instructions, the value of the PC is the address of the current
instruction plus 4 bytes.
For all other instructions that use labels, the value of the PC is the address of the
current instruction plus 4 bytes, with bit[1] of the result cleared to 0 to make it
word-aligned.
Your assembler might permit other syntaxes for PC-relative expressions, such as a
label plus or minus a number, or an expression of the form [PC, #number].
immediately after the instruction that updated the flags
after any number of intervening instructions that have not updated the flags.
does not execute
does not write any value to its destination register
does not affect any of the flags
does not generate any exception.
Section 34.3.1.3.5 “Program Status
All information provided in this document is subject to legal disclaimers.
Section 34.2.9.3
Rev. 2 — 19 August 2010
Table 615
Section 34.4.3.8 “Configuration and Control
for more information and restrictions when using
Register”. Some instructions update all flags, and
Chapter 34: Appendix: Cortex-M3 user guide
for a list of the suffixes to add to instructions
UM10360
© NXP B.V. 2010. All rights reserved.
Register”.
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