LPC1767FBD100,551 NXP Semiconductors, LPC1767FBD100,551 Datasheet - Page 721

• Manufacturer Part Number: LPC1767FBD100,551
• Description: IC ARM CORTEX MCU 512K 100-LQFP
• Manufacturer: NXP Semiconductors
• Series: LPC17xxr

Specifications of LPC1767FBD100,551

• Core Processor: ARM® Cortex-M3™
• Core Size: 32-Bit
• Speed: 100MHz
• Connectivity: Ethernet, I²C, IrDA, Microwire, SPI, SSI, UART/USART
• Peripherals: Brown-out Detect/Reset, DMA, I²S, Motor Control PWM, POR, PWM, WDT
• Number Of I /o: 70
• Program Memory Size: 512KB (512K x 8)
• Program Memory Type: FLASH
• Ram Size: 64K x 8
• Voltage - Supply (vcc/vdd): 2.4 V ~ 3.6 V
• Data Converters: A/D 8x12b, D/A 1x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 100-LQFP
• Processor Series: LPC17
• Core: ARM Cortex M3
• 3rd Party Development Tools: MDK-ARM, RL-ARM, ULINK2, MCB1760, MCB1760U, MCB1760UME
• For Use With: 622-1005 - USB IN-CIRCUIT PROG ARM7 LPC2K
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Details
• Other names: 568-4967; 935289808551

NXP Semiconductors
UM10360
User manual
34.2.10.7.1 Syntax
34.2.10.7.2 Operation
34.2.10.7.3 Restrictions
34.2.10.7.4 Condition flags
34.2.10.7.5 Examples
34.2.10.7 MSR
Move the contents of a general-purpose register into the specified special register.
MSR{cond} spec_reg, Rn
where:
cond is an optional condition code, see
Rn is the source register.
spec_reg can be any of: APSR, IPSR, EPSR, IEPSR, IAPSR, EAPSR, PSR, MSP, PSP, PRIMASK, BASEPRI,
BASEPRI_MAX, FAULTMASK, or CONTROL.
The register access operation in MSR depends on the privilege level. Unprivileged software
can only access the APSR, see
access all special registers.
In unprivileged software writes to unallocated or execution state bits in the PSR are
ignored.
Note
When you write to BASEPRI_MAX, the instruction writes to BASEPRI only if either:
See
Rn must not be SP and must not be PC.
This instruction updates the flags explicitly based on the value in Rn.
•
•
Rn is non-zero and the current BASEPRI value is 0
Rn is non-zero and less than the current BASEPRI value.
Section
MSR CONTROL, R1 ; Read R1 value and write it to the CONTROL register
34.2.10.6.
All information provided in this document is subject to legal disclaimers.
Rev. 2 — 19 August 2010
Table 628 “APSR bit
Section 34.2.3.7 “Conditional
Chapter 34: Appendix: Cortex-M3 user guide
assignments”. Privileged software can
execution”.
UM10360
© NXP B.V. 2010. All rights reserved.
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