LPC1767FBD100,551 NXP Semiconductors, LPC1767FBD100,551 Datasheet - Page 267
LPC1767FBD100,551
Manufacturer Part Number
LPC1767FBD100,551
Description
IC ARM CORTEX MCU 512K 100-LQFP
Manufacturer
NXP Semiconductors
Series
LPC17xxr
Datasheets
1.LPC1767FBD100551.pdf
(2 pages)
2.LPC1767FBD100551.pdf
(840 pages)
3.LPC1767FBD100551.pdf
(65 pages)
Specifications of LPC1767FBD100,551
Core Processor
ARM® Cortex-M3™
Core Size
32-Bit
Speed
100MHz
Connectivity
Ethernet, I²C, IrDA, Microwire, SPI, SSI, UART/USART
Peripherals
Brown-out Detect/Reset, DMA, I²S, Motor Control PWM, POR, PWM, WDT
Number Of I /o
70
Program Memory Size
512KB (512K x 8)
Program Memory Type
FLASH
Ram Size
64K x 8
Voltage - Supply (vcc/vdd)
2.4 V ~ 3.6 V
Data Converters
A/D 8x12b, D/A 1x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
100-LQFP
Processor Series
LPC17
Core
ARM Cortex M3
3rd Party Development Tools
MDK-ARM, RL-ARM, ULINK2, MCB1760, MCB1760U, MCB1760UME
For Use With
622-1005 - USB IN-CIRCUIT PROG ARM7 LPC2K
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Lead Free Status / Rohs Status
Details
Other names
568-4967
935289808551
935289808551
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
LPC1767FBD100,551
Manufacturer:
NXP Semiconductors
Quantity:
10 000
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UM10360
User manual
10. Software tests the FE bit and finds that the active buffer (B_2) is empty (FE=0).
11. Both B_1 and B_2 are empty. Software waits for the next endpoint interrupt to occur.
The following example illustrates how double buffering works for a Bulk IN endpoint in
Slave mode:
Assume that both buffer 1 (B_1) and buffer 2 (B_2) are empty and that the active buffer is
B_1. The interrupt on NAK feature is enabled.
10. Software has no more packets to send, so it simply clears the interrupt.
5. Software sends the SIE Select Endpoint command to read the Select Endpoint
6. The host re-sends the third packet which device hardware places in B_1. An endpoint
7. Software finishes reading the second packet from B_2 and sends a SIE Clear Buffer
8. Software responds to the endpoint interrupt by clearing it and begins reading the third
9. Software finishes reading the third packet from B_1 and sends a SIE Clear Buffer
1. The host requests a data packet by sending an IN token packet. The device responds
2. Software clears the endpoint interrupt. The device has three packets to send.
3. Software sends the SIE Select Endpoint command to read the Select Endpoint
4. Software waits for the endpoint interrupt to occur.
5. The device successfully sends the packet in B_1 and clears the buffer. An endpoint
6. Software clears the endpoint interrupt. Software fills B_1 with the third packet and
7. The device successfully sends the second packet from B_2 and generates an
8. Software has no more packets to send, so it simply clears the interrupt.
9. The device successfully sends the third packet from B_1 and generates an endpoint
Register and test the FE bit. Software finds that the active buffer (B_2) has data
(FE=1). Software clears the endpoint interrupt and begins reading the contents of
B_2.
interrupt is generated.
command to free B_2 to receive another packet. B_1 becomes the active buffer.
Software waits for the next endpoint interrupt to occur (it already has been generated
back in step 6).
packet from B_1.
command to free B_1 to receive another packet. B_2 becomes the active buffer.
The active buffer is now B_2. The next data packet sent by the host will be placed in
B_2.
with a NAK and generates an endpoint interrupt.
Software fills B_1 with the first packet and sends a SIE Validate Buffer command. The
active buffer is switched to B_2.
Register and test the FE bit. It finds that B_2 is empty (FE=0) and fills B_2 with the
second packet. Software sends a SIE Validate Buffer command, and the active buffer
is switched to B_1.
interrupt occurs.
validates it using the SIE Validate Buffer command. The active buffer is switched to
B_2.
endpoint interrupt.
interrupt.
All information provided in this document is subject to legal disclaimers.
Rev. 2 — 19 August 2010
Chapter 11: LPC17xx USB device controller
UM10360
© NXP B.V. 2010. All rights reserved.
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