LPC1767FBD100,551 NXP Semiconductors, LPC1767FBD100,551 Datasheet - Page 686
![IC ARM CORTEX MCU 512K 100-LQFP](/photos/6/65/66516/568-100-lqfp_sot407-1_sml.jpg)
LPC1767FBD100,551
Manufacturer Part Number
LPC1767FBD100,551
Description
IC ARM CORTEX MCU 512K 100-LQFP
Manufacturer
NXP Semiconductors
Series
LPC17xxr
Datasheets
1.LPC1767FBD100551.pdf
(2 pages)
2.LPC1767FBD100551.pdf
(840 pages)
3.LPC1767FBD100551.pdf
(65 pages)
Specifications of LPC1767FBD100,551
Core Processor
ARM® Cortex-M3™
Core Size
32-Bit
Speed
100MHz
Connectivity
Ethernet, I²C, IrDA, Microwire, SPI, SSI, UART/USART
Peripherals
Brown-out Detect/Reset, DMA, I²S, Motor Control PWM, POR, PWM, WDT
Number Of I /o
70
Program Memory Size
512KB (512K x 8)
Program Memory Type
FLASH
Ram Size
64K x 8
Voltage - Supply (vcc/vdd)
2.4 V ~ 3.6 V
Data Converters
A/D 8x12b, D/A 1x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
100-LQFP
Processor Series
LPC17
Core
ARM Cortex M3
3rd Party Development Tools
MDK-ARM, RL-ARM, ULINK2, MCB1760, MCB1760U, MCB1760UME
For Use With
622-1005 - USB IN-CIRCUIT PROG ARM7 LPC2K
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Lead Free Status / Rohs Status
Details
Other names
568-4967
935289808551
935289808551
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
LPC1767FBD100,551
Manufacturer:
NXP Semiconductors
Quantity:
10 000
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NXP Semiconductors
UM10360
User manual
34.2.5.5.1 Syntax
34.2.5.5.2 Operation
34.2.5.5.3 Restrictions
34.2.5.5.4 Condition flags
34.2.5.5.5 Examples
34.2.5.5 CMP and CMN
Compare and Compare Negative.
CMP{cond} Rn, Operand2
CMN{cond} Rn, Operand2
where:
cond is an optional condition code, see
Rn is the register holding the first operand.
Operand2 is a flexible second operand. See Flexible second operand on page 3-10for
details of the options.
These instructions compare the value in a register with Operand2. They update the
condition flags on the result, but do not write the result to a register.
The CMP instruction subtracts the value of Operand2 from the value in Rn. This is the same
as a SUBS instruction, except that the result is discarded.
The CMN instruction adds the value of Operand2 to the value in Rn. This is the same as an
ADDS instruction, except that the result is discarded.
In these instructions:
These instructions update the N, Z, C and V flags according to the result.
•
•
do not use PC
Operand2 must not be SP.
CMP
CMN
CMPGT
All information provided in this document is subject to legal disclaimers.
R2, R9
R0, #6400
SP, R7, LSL #2
Rev. 2 — 19 August 2010
Section
Chapter 34: Appendix: Cortex-M3 user guide
34.2.3.7.
UM10360
© NXP B.V. 2010. All rights reserved.
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