IPR-HPMCII Altera, IPR-HPMCII Datasheet - Page 103

• Manufacturer Part Number: IPR-HPMCII
• Description: IP CORE Renewal Of IP-HPMCII
• Manufacturer: Altera

Specifications of IPR-HPMCII

• Software Application: IP CORE, Memory Controllers, SDRAM
• Supported Families: Arria II GX, HardCopy III, Stratix III, Stratix IV
• Core Architecture: FPGA
• Core Sub-architecture: Arria, HardCopy, Stratix
• Rohs Compliant: NA
• Lead Free Status / RoHS Status: na

Chapter 6: Functional Description—High-Performance Controller
Block Description
December 2010 Altera Corporation
Figure 6–4
HPC supports a local size of 1 and 2.
Figure 6–4. Partial Write for HPC
Note to
(1) R represents the internal read-back memory data during the read-modify-write process.
Partial Bursts
DIMMs that do not have the DM pins do not support partial bursts. A minimum of
eight words must be written to the memory at the same time.
Figure 6–5
Figure 6–5. Partial Burst for HPC
ECC Latency
Using the ECC results in the following latency changes:
■
■
Local Burst Length 1
For a local burst length of 1, the write latency increases by one clock cycle; the read
latency increases by one clock cycle (including checking and correction).
A partial write results in a read followed by write in the ECC logic, so latency
depends on the time the controller takes to fetch the data from the particular address.
local_address
Local Burst Length 1
Local Burst Length 2
local_wdata
local_address
local_size
mem_dm
mem_dq
local_be
local_wdata
Figure
local_size
mem_dm
mem_dq
local_be
shows the partial write operation for HPC. The half-rate DDR3 SDRAM
shows the partial burst operation for HPC.
6–4:
01234567
X1
0
01234567
2
X1
0
1
89ABCDEF
XF
1
Section II. DDR3 SDRAM Controller with ALTMEMPHY IP User Guide
67
External Memory Interface Handbook Volume 3
R
R
67
R
45
EF
CD
23
AB
01
89
6–9