IPR-HPMCII Altera, IPR-HPMCII Datasheet - Page 88

• Manufacturer Part Number: IPR-HPMCII
• Description: IP CORE Renewal Of IP-HPMCII
• Manufacturer: Altera

Specifications of IPR-HPMCII

• Software Application: IP CORE, Memory Controllers, SDRAM
• Supported Families: Arria II GX, HardCopy III, Stratix III, Stratix IV
• Core Architecture: FPGA
• Core Sub-architecture: Arria, HardCopy, Stratix
• Rohs Compliant: NA
• Lead Free Status / RoHS Status: na

5–36
Figure 5–19. Word-Unaligned Writes
Notes to
(1) Alternative word-unaligned chip select (ctl_cs_n).
(2) As with word- aligned writes, ctl_dqs_burst is asserted one memory clock cycle before ctl_wdata_valid. You can see ctl_dqs_burst is
(3) The latency between ctl_cs_n being asserted and ctl_wdata_valid going high is effectively ctl_wlat (in this example, two) controller clock
(4) Only the upper half is valid (as the ctl_wdata_valid signal demonstrates, there is one ctl_wdata_valid bit to two 8-bit words). The write
(5) The 0504 here is residual from the previous clock cycle. In the same way that only the upper half of the write data is used for the first beat of the
External Memory Interface Handbook Volume 3
Section II. DDR3 SDRAM Controller with ALTMEMPHY IP User Guide
ctl_wdata_valid
ctl_dqs_burst
11 in the same cycle where ctl_wdata_valid is 10. The LSB of these two becomes the first value the signal takes in the mem_clk domain. You
can see that ctl_dqs_burst has the necessary one mem_clk cycle lead on ctl_wdata_valid.
(ctl_clk) cycles. This can be thought of in terms of relative memory clock (mem_clk) cycles, in which case the latency is four mem_clk cycles.
data bits go out on the bus in order, least significant byte first. So for a continuous burst of write data on the DQ pins, the most significant half of
write data is used, which goes out on the bus last and is therefore contiguous with the following data. The converse is true for the end of the burst.
Write data is spread across three controller clock (ctl_clk) cycles, but still only four memory clock (mem_clk) cycles. However, in relative
memory clock cycles the latency is equivalent in the word-aligned and word-unaligned cases.
write, only the lower half of the write data is used in the last beat of the write. These upper bits can be driven to any value in this alignment.
mem_cs_n
command
mem_dqs
ctl_cas_n
ctl_wdata
ctl_ras_n
mem_clk
ctl_we_n
mem_dq
ctl_cs_n
Memory
Interface
ctl_addr
ctl_wlat
Figure
ctl_clk
ctl_ba
5–19:
10 10
11 11
01 01
01 01
00000000
00000000
0000000
0000000
Figure 5–19
00 00
00 00
10
ACT
ACT
and
11
01000000 05040302 05040706 09080706 0d0c0b0a
(1)
020000
Figure 5–20
10
11
10
11
(2)
show spaced word-unaligned writes and reads.
(3)
01
01
00
2
(4)
10
00
00
11
(5)
11
Chapter 5: Functional Description—ALTMEMPHY
020008
WR
01
01
11
December 2010 Altera Corporation
0d0c0f0e
PHY-to-Controller Interfaces
00
00