IPR-HPMCII Altera, IPR-HPMCII Datasheet - Page 51

• Manufacturer Part Number: IPR-HPMCII
• Description: IP CORE Renewal Of IP-HPMCII
• Manufacturer: Altera

Specifications of IPR-HPMCII

• Software Application: IP CORE, Memory Controllers, SDRAM
• Supported Families: Arria II GX, HardCopy III, Stratix III, Stratix IV
• Core Architecture: FPGA
• Core Sub-architecture: Arria, HardCopy, Stratix
• Rohs Compliant: NA
• Lead Free Status / RoHS Status: na

Chapter 4: Compiling and Simulating
Simulating the Design
December 2010 Altera Corporation
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If you are simulating your ALTMEMPHY-based design with a Denali model, Altera
recommends that you use full calibration mode.
For more information about simulation, refer to the
the External Memory Interface Handbook.
Full calibration—across all pins and chip selects. This option allows for longer
simulation time.
Available for ×4 and ×8 DDR3 SDRAM between 300 MHz and 533 MHz. You
cannot use the wizard-generated memory model, if you select Full Calibration.
You must use a memory-vendor provided memory model that supports write
leveling calibration.
Section II. DDR3 SDRAM Controller with ALTMEMPHY IP User Guide
Simulation
External Memory Interface Handbook Volume 3
section in volume 4 of
4–5