IPR-HPMCII Altera, IPR-HPMCII Datasheet - Page 112

• Manufacturer Part Number: IPR-HPMCII
• Description: IP CORE Renewal Of IP-HPMCII
• Manufacturer: Altera

Specifications of IPR-HPMCII

• Software Application: IP CORE, Memory Controllers, SDRAM
• Supported Families: Arria II GX, HardCopy III, Stratix III, Stratix IV
• Core Architecture: FPGA
• Core Sub-architecture: Arria, HardCopy, Stratix
• Rohs Compliant: NA
• Lead Free Status / RoHS Status: na

6–18
Table 6–13. Local Interface Signals (Part 2 of 4)
External Memory Interface Handbook Volume 3
Section II. DDR3 SDRAM Controller with ALTMEMPHY IP User Guide
local_burstbegin
local_read_req
local_refresh_req
local_size[]
local_wdata[]
local_write_req
local_autopch_req
Signal Name
Input
Direction
Input
Input
Input
Input
Input
Input
Avalon burst begin strobe, which indicates the beginning of an Avalon burst.
This signal is only available when the local interface is an Avalon-MM interface
and the memory burst length is greater than 2. Unlike all other Avalon-MM
signals, the burst begin signal does not stay asserted if local_ready is
deasserted.
For write transactions, assert this signal at the beginning of each burst transfer
and keep this signal high for one cycle per burst transfer, even if the slave has
deasserted the local_ready signal. After the slave deasserts the
local_ready signal, the master keeps all the write request signals asserted
until the local_ready signal becomes high again.
For read transactions, assert this signal for one clock cycle when read request
is asserted and the local_address from which the data should be read is
given to the memory. After the slave deasserts the local_ready signal
(waitrequest_n in Avalon), the master keeps all the read request signals
asserted until the local_ready signal becomes high again.
Read request signal. You cannot assert the read request signal before the
reset_phy_clk_n signal goes high.
User-controlled refresh request. If Enable user auto-refresh controls is turned
on, local_refresh_req becomes available and you are responsible for
issuing sufficient refresh requests to meet the memory requirements. This
option allows complete control over when refreshes are issued to the memory
including ganging together multiple refresh commands. Refresh requests take
priority over read and write requests unless they are already being processed.
Controls the number of beats in the requested read or write access to memory,
encoded as a binary number. The DDR3 SDRAM HPC supports burst lengths
of 1 and 2 on the local side interface.
Write data bus. The width of local_wdata is twice that of the memory data
bus for a full rate controller; four times the memory data bus for a half rate
controller.
Write request signal. You cannot assert the write request signal before the
reset_phy_clk_n signal goes high.
User control of precharge. If Enable Auto-Precharge Control is turned on,
local_autopch_req becomes available and you can request the controller to
issue an auto-precharge write or auto-precharge read command. These
commands cause the memory to issue a precharge command to the current
bank at the appropriate time without an explicit precharge command from the
controller. This is particularly useful if you know the current read or write is the
last one you intend to issue to the currently open row. The next time you need
to use that bank, the access could be quicker as the controller does not need to
precharge the bank before activating the row you wish to access.
Chapter 6: Functional Description—High-Performance Controller
Description
December 2010 Altera Corporation
Top-level Signals Description