IPR-HPMCII Altera, IPR-HPMCII Datasheet - Page 36

• Manufacturer Part Number: IPR-HPMCII
• Description: IP CORE Renewal Of IP-HPMCII
• Manufacturer: Altera

Specifications of IPR-HPMCII

• Software Application: IP CORE, Memory Controllers, SDRAM
• Supported Families: Arria II GX, HardCopy III, Stratix III, Stratix IV
• Core Architecture: FPGA
• Core Sub-architecture: Arria, HardCopy, Stratix
• Rohs Compliant: NA
• Lead Free Status / RoHS Status: na

3–8
Table 3–4. DDR3 SDRAM Initialization Options (Part 3 of 3)
Table 3–5. DDR3 SDRAM Timing Parameter Settings (Part 1 of 3)
External Memory Interface Handbook Volume 3
Section II. DDR3 SDRAM Controller with ALTMEMPHY IP User Guide
Memory auto self refresh
method
Memory self refresh range
Time to hold memory reset
before beginning calibration
t
t
t
t
t
t
t
t
INIT
MRD
RAS
RCD
RP
REFI
RFC
WR
Parameter Name
Parameter Name
0–1000000
0.001–
1000
2–39
8–200
4–65
4–65
1–65534
14–1651
4–65
reference (SRT) or
ASR enable
Manual SR
Normal or
(Optional)
Extended
Range
Range
µs
µs
ns
ns
ns
ns
µs
ns
ns
Units
Units
—
—
Minimum time to hold the reset after a power cycle
before issuing the MRS commands during the DDR3
SDRAM device initialization process.
Minimum memory initialization time. After reset, the
controller does not issue any commands to the
memory during this period.
Minimum load mode register command period. The
controller waits for this period of time after issuing a
load mode register command before issuing any other
commands.
t
high-performance controller and in terms of t
in Micron's device datasheet. Convert t
multiplying the number of cycles specified in the
datasheet times t
frequency and not the memory device's t
Minimum active to precharge time. The controller waits
for this period of time after issuing an active command
before issuing a precharge command to the same bank.
Minimum active to read-write time. The controller does
not issue read or write commands to a bank during this
period of time after issuing an active command.
Minimum precharge command period. The controller
does not access the bank for this period of time after
issuing a precharge command.
Maximum interval between refresh commands. The
controller performs regular refresh at this interval
unless user-controlled refresh is turned on.
Minimum autorefresh command period. The length of
time the controller waits before doing anything else
after issuing an auto-refresh command.
Minimum write recovery time. The controller waits for
this period of time after the end of a write transaction
before issuing a precharge command.
Sets the auto self-refresh method for the memory
device. The DDR3 SDRAM Controller with ALTMEMPHY
IP currently does not support the ASR option that you
need for extended temperature memory self-refresh.
Determines the temperature range for self refresh. You
need to also use the optional auto self refresh option
when using this option. The Altera controller currently
does not support the extended temperature self-refresh
operation.
MRD
(Note 1)
is specified in ns in the DDR3 SDRAM
CK
, where t
Description
Description
December 2010 Altera Corporation
CK
ALTMEMPHY Parameter Settings
Chapter 3: Parameter Settings
is the memory operation
MRD
CK
.
to ns by
CK
cycles