IPR-HPMCII Altera, IPR-HPMCII Datasheet - Page 87

• Manufacturer Part Number: IPR-HPMCII
• Description: IP CORE Renewal Of IP-HPMCII
• Manufacturer: Altera

Specifications of IPR-HPMCII

• Software Application: IP CORE, Memory Controllers, SDRAM
• Supported Families: Arria II GX, HardCopy III, Stratix III, Stratix IV
• Core Architecture: FPGA
• Core Sub-architecture: Arria, HardCopy, Stratix
• Rohs Compliant: NA
• Lead Free Status / RoHS Status: na

Chapter 5: Functional Description—ALTMEMPHY
PHY-to-Controller Interfaces
Figure 5–18. Word-Aligned Reads
Notes to
(1) For AFI, ctl_doing_rd is required to be asserted one memory clock cycle before chip select (ctl_cs_n) is asserted. In the half-rate ctl_clk
(2) AFI requires that ctl_doing_rd is driven for the duration of the read. In this example, it is driven to 11 for two half-rate ctl_clks, which equates
(3) The ctl_rdata_valid returns 15 (ctl_rlat) controller clock (ctl_clk) cycles after ctl_doing_rd is asserted. Returned is when the
(4) Observe the alignment of returned read data with respect to data on the bus.
December 2010 Altera Corporation
ctl_rdata_valid
ctl_doing_rd
domain, this requirement manifests as the controller driving 11 (as opposed to the 01) on ctl_doing_rd.
to driving to 1, for the four memory clock cycles of this four-beat burst.
ctl_rdata_valid signal is observed at the output of a register within the controller. A controller can use the ctl_rlat value to determine when
to register to returned data, but this is unnecessary as the ctl_rdata_valid is provided for the controller to use as an enable when registering
read data.
mem_cs_n
command
mem_dqs
ctl_cas_n
ctl_ras_n
ctl_we_n
mem_clk
mem_dq
ctl_rdata
ctl_cs_n
Memory
Interface
ctl_addr
ctl_rlat
ctl_dm
Figure
ctl_clk
ctl_ba
5–18:
00 00
11 11
00 00
01
ACT
0000000
11
11
00
(1)
01
11
(2)
FFFFFFFF
FFFFFFFF
(2)
00 00
Section II. DDR3 SDRAM Controller with ALTMEMPHY IP User Guide
11
0
11
00
15
0020008
RD
11
00
External Memory Interface Handbook Volume 3
11
00
(3)
(4)
11
00
5–35