IPR-HPMCII Altera, IPR-HPMCII Datasheet - Page 175

• Manufacturer Part Number: IPR-HPMCII
• Description: IP CORE Renewal Of IP-HPMCII
• Manufacturer: Altera

Specifications of IPR-HPMCII

• Software Application: IP CORE, Memory Controllers, SDRAM
• Supported Families: Arria II GX, HardCopy III, Stratix III, Stratix IV
• Core Architecture: FPGA
• Core Sub-architecture: Arria, HardCopy, Stratix
• Rohs Compliant: NA
• Lead Free Status / RoHS Status: na

Document Revision History
How to Contact Altera
December 2010 Altera Corporation
December 2010
July 2010
February 2010
February 2010
November 2009
November 2009
Date
2.1
2.0
1.3
1.2
1.1
1.0
Version
This chapter provides additional information about the document and Altera.
The following table shows the revision history for this document.
To locate the most up-to-date information about Altera products, refer to the
following table.
Technical support
Technical training
Product literature
Non-technical support (General)
Note to Table:
(1) You can also contact your local Altera sales office or sales representative.
Updated for 10.1.
■
■
Corrected typos.
■
■
■
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Minor corrections.
First published.
Added information for new GUI parameters: Controller latency, Enable reduced bank
tracking for area optimization, and Number of banks to track.
Removed information about IP Advisor. This feature is removed from the DDR3 SDRAM
IP support for version 10.0.
Full support for Stratix IV devices.
Added information for Register Control Word parameters.
Added descriptions for mem_ac_parity, mem_err_out_n, and parity_error_n
signals.
Added timing diagrams for initialization and calibration stages for HPC.
Contact
(Software Licensing)
(1)
Contact Method
Website
Website
Website
Email
Email
Email
Section II. DDR3 SDRAM Controller with ALTMEMPHY IP User Guide
Changes
www.altera.com/support
www.altera.com/training
[e-mail]
www.altera.com/literature
[e-mail]
[e-mail]
Additional Information
External Memory Interface Handbook Volume 3
Address