IPR-HPMCII Altera, IPR-HPMCII Datasheet - Page 67

• Manufacturer Part Number: IPR-HPMCII
• Description: IP CORE Renewal Of IP-HPMCII
• Manufacturer: Altera

Specifications of IPR-HPMCII

• Software Application: IP CORE, Memory Controllers, SDRAM
• Supported Families: Arria II GX, HardCopy III, Stratix III, Stratix IV
• Core Architecture: FPGA
• Core Sub-architecture: Arria, HardCopy, Stratix
• Rohs Compliant: NA
• Lead Free Status / RoHS Status: na

Chapter 5: Functional Description—ALTMEMPHY
Block Description
Table 5–1. DDR3 SDRAM Clocking in Arria II GX Devices (Part 2 of 2)
December 2010 Altera Corporation
ac_clk_2x
cs_n_clk_2x
resync_clk_2x
measure_clk_2x
Note to
(1) The _1x clock represents a frequency that is half of the memory clock frequency; the _2x clock represents the memory clock frequency.
Clock Name
Table
5–1:
(1)
Postscale
Counter
C3
C3
C4
C5
(Degrees)
Calibrated
Calibrated
Phase
–90°
–90°
Clock Rate
Full-Rate
Full-Rate
Full-Rate
Full-Rate
Section II. DDR3 SDRAM Controller with ALTMEMPHY IP User Guide
Network Type
Global
Global
Global
Global
Clock
External Memory Interface Handbook Volume 3
Address and command clock.
The ac_clk_2x clock is derived
from either mem_clk_2x (when
you choose 0° or 180° phase
shift) or write_clk_2x (when you
choose 90° or 270° phase shift).
Refer to
Datapath” on page 5–11
illustrations of the address and
command clock relationship with
the mem_clk_2x or
write_clk_2x signals.
Memory chip-select clock.
The cs_n_clk_2x clock is derived
from ac_clk_2x.
Clocks the resynchronization
registers after the capture
registers. Its phase is adjusted to
the center of the data valid window
across all the DQS-clocked DDIO
groups.
This clock is for VT tracking. This
free-running clock measures
relative phase shifts between the
internal clock(s) and those being
fed back through a mimic path. As
a result, the ALTMEMPHY
megafunction can track VT effects
on the FPGA and compensate for
the effects.
“Address and Command
Notes
for
5–15