IPR-HPMCII Altera, IPR-HPMCII Datasheet - Page 41

• Manufacturer Part Number: IPR-HPMCII
• Description: IP CORE Renewal Of IP-HPMCII
• Manufacturer: Altera

Specifications of IPR-HPMCII

• Software Application: IP CORE, Memory Controllers, SDRAM
• Supported Families: Arria II GX, HardCopy III, Stratix III, Stratix IV
• Core Architecture: FPGA
• Core Sub-architecture: Arria, HardCopy, Stratix
• Rohs Compliant: NA
• Lead Free Status / RoHS Status: na

Chapter 3: Parameter Settings
DDR3 SDRAM Controller with ALTMEMPHY Parameter Settings
Table 3–7. ALTMEMPHY Board Settings
DDR3 SDRAM Controller with ALTMEMPHY Parameter Settings
December 2010 Altera Corporation
Number of slots/discrete devices
CK/CK# slew rate (differential)
Addr/command slew rate
DQ/DQS# slew rate (differential)
DQ slew rate
Addr/command eye reduction
(setup)
Addr/command eye reduction
(hold)
DQ eye reduction
Delta DQS arrival time
Min CK/DQS skew to DIMM
Max CK/DQS skew to DIMM
Max skew between
DIMMs/devices
Max skew within DQS group
Max skew between DQS groups
Addr/command to CK skew
Parameter Name
Board Settings
Click Next or the Board Settings tab to set the options described in
board settings parameters are set to model the board level effects in the timing
analysis. The options are available if you choose Arria II GX or Stratix IV device for
your interface. Otherwise, the options are disabled.
The Parameter Settings page in the DDR3 SDRAM Controller with ALTMEMPHY
parameter editor
■
■
■
■
Memory Settings
PHY Settings
Board Settings
Controller Settings
Units
V/ns
V/ns
V/ns
V/ns
—
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
(Figure
3–3) allows you to parameterize the following settings:
Sets the single-rank or multi-rank configuration.
Sets the differential slew rate for the CK and CK# signals.
Sets the slew rate for the address and command signals.
Sets the differential slew rate for the DQ and DQS# signals.
Sets the slew rate for the DQ signals.
Sets the reduction in the eye diagram on the setup side due to the
ISI on the address and command signals.
Sets the reduction in the eye diagram on the hold side due to the ISI
on the address and command signals.
Sets the total reduction in the eye diagram on the setup side due to
the ISI on the DQ signals.
Sets the increase of variation on the range of arrival times of DQS
due to ISI.
Sets the minimum skew between the CK signal and any DQS signal
when arriving at the same DIMM over all DIMMs.
Sets the maximum skew between the CK signal and any DQS signal
when arriving at the same DIMM over all DIMMs.
Sets the largest skew or propagation delay on the DQ signals
between ranks, especially true for DIMMs in different slots.
Sets the largest skew between the DQ pins in a DQS group.
Sets the largest skew between DQS signals in different DQS groups.
Sets the skew or propagation delay between the CK signal and the
address and command signals. The positive values represent the
address and command signals that are longer than the CK signals,
and the negative values represent the address and command signals
that are shorter than the CK signals.
Section II. DDR3 SDRAM Controller with ALTMEMPHY IP User Guide
Description
External Memory Interface Handbook Volume 3
Table
3–7. The
3–13