IPR-HPMCII Altera, IPR-HPMCII Datasheet - Page 174

• Manufacturer Part Number: IPR-HPMCII
• Description: IP CORE Renewal Of IP-HPMCII
• Manufacturer: Altera

Specifications of IPR-HPMCII

• Software Application: IP CORE, Memory Controllers, SDRAM
• Supported Families: Arria II GX, HardCopy III, Stratix III, Stratix IV
• Core Architecture: FPGA
• Core Sub-architecture: Arria, HardCopy, Stratix
• Rohs Compliant: NA
• Lead Free Status / RoHS Status: na

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External Memory Interface Handbook Volume 3
Section II. DDR3 SDRAM Controller with ALTMEMPHY IP User Guide
13. The controller returns the first read data to the user by asserting the
local_rdata_valid signal when there is valid read data on the local_rdata bus.
If the ECC logic is disabled, there is no delay between the afi_rdata and the
local_rdata buses. If there is ECC logic in the controller, there is one or three clock
cycles of delay between the afi_rdata and local_rdata buses.
DDR3 High-Performance Controllers II
December 2010 Altera Corporation
Chapter 9: Timing Diagrams