IPR-HPMCII Altera, IPR-HPMCII Datasheet - Page 35

• Manufacturer Part Number: IPR-HPMCII
• Description: IP CORE Renewal Of IP-HPMCII
• Manufacturer: Altera

Specifications of IPR-HPMCII

• Software Application: IP CORE, Memory Controllers, SDRAM
• Supported Families: Arria II GX, HardCopy III, Stratix III, Stratix IV
• Core Architecture: FPGA
• Core Sub-architecture: Arria, HardCopy, Stratix
• Rohs Compliant: NA
• Lead Free Status / RoHS Status: na

Chapter 3: Parameter Settings
ALTMEMPHY Parameter Settings
Table 3–4. DDR3 SDRAM Initialization Options (Part 2 of 3)
December 2010 Altera Corporation
Enable the DLL in the
memory devices
ODT Rtt nominal value
Dynamic ODT (Rtt_WR) value
Output driver impedance
Memory CAS latency setting
Memory additive CAS latency
setting
Memory write CAS latency
setting (CWL)
Memory partial array self
refresh
Parameter Name
{BA[2:0]=000,001,
{BA[2:0]=000,001}
{BA[2:0]=010,011,
100,101,110,111},
{BA[2:0]=100,101,
RZQ/6 (Reserved)
Dynamic ODT off,
5.0, 6.0, 7.0, 8.0,
5.0, 6.0, 7.0, 8.0
Disable, CL – 1,
{BA[2:0]=000},
Three Quarters
RZQ/4, RZQ/2,
{BA[2:0]=110,
{BA[2:0]=111}
RZQ/4, RZQ/2
Quarter array
Quarter array
ODT disable,
Eighth array
Eighth array
Yes or No
Full array,
Half array
010,011},
Half array
110,111},
or RZQ/7
9.0, 10.0
Range
CL – 2
RZQ/6
array
111},
,
cycles
cycles
cycles
Units
—
—
W
W
W
Section II. DDR3 SDRAM Controller with ALTMEMPHY IP User Guide
Enables the DLL in the memory device when set to Yes.
You must always enable the DLL in the memory device
as Altera does not guarantee any ALTMEMPHY
operation when the DLL is turned off. All timings from
the memory devices are invalid when the DLL is turned
off.
RZQ in DDR3 SDRAM interfaces are set to 240 Ω. Sets
the on-die termination (ODT) value to either 60 Ω
(RZQ/4), 120 Ω (RZQ/2), or 40 Ω (RZQ/6). Set this to
ODT disable if you are not planning to use ODT. For a
single-ranked DIMM, set this to RZQ/4.
RZQ in DDR3 SDRAM interfaces are set to 240 Ω. Sets
the memory ODT value during write operations to 60 Ω
(RZQ/4) or 120 Ω (RZQ/2). As ALTMEMPHY only
supports single rank DIMMs, you do not need this
option (set to Dynamic ODT off).
RZQ in DDR3 SDRAM interfaces are set to 240 Ω. Sets
the output driver impedance from the memory device.
Some devices may not have RZQ/6 available as an
option. Be sure to check the memory device datasheet
before choosing this option.
Sets the delay in clock cycles from the read command
to the first output data from the memory.
Allows you to add extra latency in addition to the CAS
latency setting.
Sets the delay in clock cycles from the write command
to the first expected data to the memory.
Determine whether you want to self-refresh only certain
arrays instead of the full array. According to the DDR3
SDRAM specification, data located in the array beyond
the specified address range are lost if self refresh is
entered when you use this. This option is not supported
by the DDR3 SDRAM Controller with ALTMEMPHY IP,
so set to Full Array if you are using the Altera
controller.
External Memory Interface Handbook Volume 3
Description
3–7