IPR-HPMCII Altera, IPR-HPMCII Datasheet - Page 106

• Manufacturer Part Number: IPR-HPMCII
• Description: IP CORE Renewal Of IP-HPMCII
• Manufacturer: Altera

Specifications of IPR-HPMCII

• Software Application: IP CORE, Memory Controllers, SDRAM
• Supported Families: Arria II GX, HardCopy III, Stratix III, Stratix IV
• Core Architecture: FPGA
• Core Sub-architecture: Arria, HardCopy, Stratix
• Rohs Compliant: NA
• Lead Free Status / RoHS Status: na

6–12
Table 6–4. ECC Registers (Part 3 of 3)
Table 6–5. Control Word Specification Register
External Memory Interface Handbook Volume 3
Section II. DDR3 SDRAM Controller with ALTMEMPHY IP User Guide
Single-bit error location
status register
Double-bit error location
status register
Bit
10
11
0
1
2
3
4
5
6
7
8
9
Name
Count single-bit error
Correct single-bit error
Double-bit error enable
Reserved
Clear all status registers
Reserved
Reserved
Counter clear on read
Corrupt ECC enable
ECC corruption type
First or last error
Clear interrupt
ECC Register Bits
Table 6–5
Name
Address
0D
0C
shows the control word specification register.
(Bits)
Size
32
32
Decoder-corrector
Decoder-corrector
Decoder-corrector
N/A
Controller
N/A
N/A
Controller
Controller
Controller
Controller
Controller
Attribute
Direction
R/W
R/W
Chapter 6: Functional Description—High-Performance Controller
00000000
00000000
Default
When 1, count single-bit errors.
When 1, correct single-bit errors.
When 1, detect all double-bit errors and
increment double-bit error counter.
Reserved for future use.
When 1, clear counters single-bit error and
double-bit error status registers for first and last
error address.
Reserved for future use.
Reserved for future use.
When 1, enables counters to clear on read
feature.
When 1, enables deliberate ECC corruption
during encoding, to test the ECC.
When 0, creates single-bit errors in all ECC
codewords; when 1, creates double-bit errors in
all ECC codewords.
When 1, stores the first error address rather
than the last error address of single-bit error or
double-bit error.
When 1, clears the interrupt.
This status register stores the occurrence
of single-bit error for each 64-bit part of
the data word in every bit (refer to
Table
cleared by writing a 1 in the respective
locations.
This status register stores the occurrence
of double-bit error for each 64-bit part of
the data word in every bit (refer to
Table
cleared by writing a 1 in the respective
locations.
6–8). These status bits can be
6–9). These status bits can be
Description
December 2010 Altera Corporation
Description
Block Description